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mitsubishi semiconductor america, inc. preliminary single-chip 8-bit cmos microcontroller M37640E8-XXXFP speci?cation ver 1.04
6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers this publication, or any parts thereof, may not be reproduced in any form without the prior written permission of mitsubishi semiconductor america, inc. (msai). the product(s) described in this publication are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the product could create a situation where personal injury or death may occur. should buyer purchase or use this product for any such unintended or unauthorized application, buyer shall indemnify and hold msai and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that msai was negligent regarding the design and manufacture of the part. information supplied by msai is believed to be accurate and reliable. msai assumes no responsibility for any errors that may appear in this publication. msai reserves the right, without notice, to make changes in device design or specifications. product is subject to availability. ?1997 mitsubishi semiconductor america, inc. rev. 1.0 internal release april 2, 1997 rev. 1.01 design spec updates july 1, 1997 rev. 1.02 design spec updates august 28, 1997 rev. 1.03 internal spec updates jan. 22, 1998 rev. 1.04 design spec updates june 2, 1998
7600 series mitsubishi M37640E8-XXXFP specification semiconductor corporation 1 overview 1.1 mcu features .................................................... 1-5 1.2 pin description and layout ................................ 1-6 2 functional description 2.1 central processing unit...................................... 2-3 2.1.1 register structure ......................................... 2-3 2.1.2 accumulator (a)........................................... 2-3 2.1.3 index registers x and y............................... 2-4 2.1.4 stack pointer................................................. 2-4 2.1.5 program counter .......................................... 2-4 2.1.6 processor status register ............................. 2-5 2.2 cpu mode registers .......................................... 2-7 2.3 oscillator circuit ................................................ 2-8 2.3.1 description ................................................... 2-8 2.3.2 frequency synthesizer circuit ................... 2-11 2.4 memory map .................................................... 2-14 2.4.1 zero page .................................................... 2-15 2.4.2 special page................................................ 2-15 2.4.3 special function registers ......................... 2-15 2.5 processor modes............................................... 2-17 2.5.1 single chip ................................................. 2-17 2.5.2 memory expansion .................................... 2-18 2.5.3 microprocessor ........................................... 2-18 2.5.4 eprom ...................................................... 2-18 2.5.5 slow memory wait .................................... 2-19 2.5.6 hold function ............................................. 2-23 2.5.7 expanded data memory access ................ 2-23 2.6 peripheral interface .......................................... 2-25 2.6.1 chip bus timing ........................................ 2-25 2.6.2 peripheral interface and access timing..... 2-26 2.7 input and output ports ..................................... 2-28 2.7.1 ports ............................................................ 2-28 2.7.1.1 i/o ports................................................ 2-29 2.7.1.2 power and ground pins ........................ 2-40 2.7.1.3 cnv ss pin ............................................. 2-40 2.7.1.4 x in and xout pins ................................. 2-40 2.7.1.5 x cin and xcout pins ............................ 2-40 2.7.1.6 reset pin............................................ 2-40 2.7.1.7 rdy pin ............................................... 2-41 2.7.1.8 dmaout pin ......................................... 2-41 2.7.1.9 f out pin.................................................. 2-41 2.7.1.10 sync out pin ....................................... 2-41 2.7.1.11 rd and wr pins................................. 2-41 2.7.1.12 lpf pin ............................................... 2-41 2.7.1.13 usb d+/d- pins ................................. 2-41 2.7.1.14 ext. cap pin ........................................ 2-41 2.7.2 port control register .................................. 2-42 2.7.3 port 2 pull-up control register .................. 2-42 2.8 interrupt control unit....................................... 2-43 2.8.1 interrupt control ......................................... 2-43 2.8.2 interrupt sequence and timing .................. 2-47 2.9 universal serial bus ......................................... 2-49 2.9.1 usb function control unit (usb fcu).... 2-50 2.9.1.1 serial interface engine ......................... 2-50 2.9.1.2 generic function interface ................... 2-50 2.9.1.3 serial engine interface unit ................. 2-50 2.9.1.4 microcontroller interface unit.............. 2-50 2.9.1.5 usb transceiver................................... 2-50 2.9.2 usb interrupts............................................ 2-51 2.9.2.1 usb function interrupt ........................ 2-51 2.9.2.2 usb sof interrupt ............................... 2-52 2.9.3 usb endpoint fifos.................................. 2-52 2.9.3.1 in (transmit) fifos............................. 2-52 2.9.3.2 out (receive) fifos............................. 2-53 2.9.4 usb special function registers................. 2-54 2.10 master cpu bus interface.............................. 2-65 2.10.1 data bus buffer status registers (dbbs0, dbbs1)....................................... 2-68 2.10.2 input data bus buffer registers (dbbin0, dbbin1)................................... 2-68 2.10.3 output data bus buffer registers (dbbout0, dbbout1)........................... 2-68 2.11 direct memory access controller.................. 2-69 2.11.1 operation .................................................. 2-70 2.11.1.1 source, destination, and transfer count register operation ............................................ 2-71 2.11.1.2 dmac transfer request sources ...... 2-71 2.11.1.3 transfer features for usb and mbi .. 2-72 2.11.1.4 dmac transfer mode ....................... 2-74 2.11.1.5 dmac transfer timing ..................... 2-74 2.12 special count source generator .................... 2-79 2.12.1 scsg operation ....................................... 2-79 2.12.2 scsg description..................................... 2-80 2.12.2.1 scsg1 ................................................ 2-80 2.12.2.2 scsg2 ................................................ 2-80 2.13 timers............................................................. 2-82 2.13.1 timer x..................................................... 2-82 2.13.1.1 read and write method...................... 2-82 2.13.1.2 count stop control ............................. 2-83 2.13.1.3 timer mode ........................................ 2-83 2.13.1.4 pulse output mode ............................. 2-83 2.13.1.5 event counter mode........................... 2-84 2.13.1.6 pulse width measurement mode........ 2-84 2.13.2 timer y..................................................... 2-84 2.13.2.1 read and write method...................... 2-85 2.13.2.2 count stop control ............................. 2-85 2.13.2.3 timer mode ........................................ 2-85 2.13.2.4 pulse period measurement mode ....... 2-86 2.13.2.5 event counter mode........................... 2-86 2.13.2.6 hl pulse-width measurement mode.. 2-86 2.13.3 timer 1 ..................................................... 2-87 2.13.3.1 timer mode ........................................ 2-87 2.13.3.2 pulse output mode ............................. 2-87 2.13.4 timer 2 ..................................................... 2-88 2.13.4.1 timer mode ........................................ 2-88 2.13.4.2 pulse output mode ............................. 2-88
mitsubishi 7600 series semiconductor corporation M37640E8-XXXFP specification 2.13.5 timer 3 ..................................................... 2-88 2.13.5.1 timer mode ........................................ 2-88 2.14 uart ............................................................. 2-90 2.14.1 baud rate selection.................................. 2-91 2.14.2 uart mode register............................... 2-93 2.14.3 uart control register............................ 2-94 2.14.4 uart baud rate register ....................... 2-94 2.14.5 uart status register .............................. 2-94 2.14.6 transmit/receive format ......................... 2-96 2.14.7 interrupts................................................... 2-98 2.14.8 clear-to send (ctsx) and request-to-send (rtsx) signals................ 2-99 2.14.9 uart address mode ............................. 2-100 2.15 serial i/o ...................................................... 2-102 2.15.1 sio control register .............................. 2-102 2.15.2 sio operation......................................... 2-102 2.16 low power modes........................................ 2-105 2.16.1 stop mode............................................... 2-105 2.16.2 wait mode .............................................. 2-106 2.17 reset ............................................................. 2-107 2.18 key-on wake-up......................................... 2-108 3 electrical characteristics 3.1 absolute maximum ratings............................... 3-3 3.2 recommended operating conditions ................. 3-4 3.3 electrical characteristics .................................... 3-6 3.4 timing requirements and switching characteristics .................................... 3-8 4 application notes 4.1 dmac ................................................................ 4-3 4.1.1 application ................................................... 4-3 4.2 uart ................................................................. 4-4 4.2.1 application ................................................... 4-4 4.3 timer .................................................................. 4-5 4.3.1 usage ............................................................ 4-5 4.4 frequency synthesizer interface ........................ 4-6 4.5 usb transceiver ................................................ 4-7 4.6 ports .................................................................... 4-8 4.7 programming notes............................................ 4-9 5 register list
mitsubishi semiconductor america, inc. preliminary chapter 1 product description 1 overview . . . . . . . . . . . . . . . . . . 1-3 1.1 mcu features . . . . . . . . . . . . 1-5 1.2 pin description and layout . . 1-6
1-2 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 1-3 1 overview the 7600 series, an enhanced family of cmos 8-bit microcontrollers, offers high-speed operation at low voltage, large internal-memory options, and a wide variety of standard peripherals. the series is code compatible with the m38000, m37200, m37400, and the m37500 series, and provides many performance enhancements to the instruction set. this device is a single chip pc peripheral microcontroller based on the universal serial bus (usb) version 1.0 specification. this device provides data exchange between a usb-equipped host computer and pc peripherals such as telephones, audio systems and digital cameras. see figure 1-1 for an application system diagram. the usb function control unit can support all four data transfer types listed in the usb specification: control, isochronous, interrupt, and bulk. each transfer type is used for controlling a different set of pc peripherals. isochronous transfers provide guaranteed bus access, a constant data rate, and error tolerance for devices such as computer-telephone integration (cti) and audio systems. interrupt transfers are designed to support human input devices (hid) that communicate small amounts of data infrequently. bulk transfers are necessary for devices such as digital cameras and scanners that communicate large amounts of data to the pc as bus bandwidth becomes free. finally, control transfers are supported and are useful for bursty, host-initiated type communication where bus management is the primary concern. figure 1-1. application system diagram frequency ram(1k) rom(32k) dmac x 2 7600 cpu uart x 2 timers sio scsg i/o ports (p0 ~ p8) bus interface control block fifos usb function control unit transceiver d+ d- (normal mcu or dma transfer) 4-24 mhz dq(7:0) s 0 , s 1 rd wr ibf 0 obf 0 48 mhz f master cpu ibf 1 obf 1 a 0 synthesizer
1-4 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers table 1-1. device feature list parameter function description number of basic instructions 71 instruction execution time (minimum) 83ns at f = 12 mhz (setting f to less than 5mhz is not recommended) clock frequency (maximum) xin = 48 mhz, xc in = 5 mhz (square wave), f = 12 mhz clock multiplier option external clock x in and xc in can be selectively divided and multiplied by x to create system internal clock f memory size rom 32k bytes ram 1k bytes input/output ports p0~p3, p5, p6, p8 i/o 8-bit x 7 (port 2 has a key-on wake-up feature) p4, p7 i/o 5-bit x 2 usb function control fifo: endpoint 0: in 16-byte out 16-byte endpoint 1: in 512-byteout 800-byte endpoint 2: in 32-byte out 32-byte endpoint 3: in 16-byte out 16-byte endpoint 4: in 16-byte out 16-byte master cpu bus interface dq(7:0), r(e), w(r/ w), s 0 , s 1 , a 0 , ibf 0 , obf 0 , ibf 1 , obf 1 ; total of 17 signals interface with master cpu (intel 8042-like interface) special count source generator(scsg) baud rate synthesizer uart x 2 7/8/9-bit character length, with cts, rts available serial i/o 8-bit clock synchronous serial i/o, supports both master and slave modes timers 8-bit x 3, 16-bit x 2 dmac 2 channels, 16 address lines, support single byte or burst transfer modes software selectable slew rate control ports p0 ~ p8 interrupts 4 external, 19 internal, 1 software, 1 system interrupts supply voltage v cc = 4.15 ~ 5.25v external memory expansion memory expansion and microprocessor mode external data memory access (edma) allows > 64 kbyte data access for instruction lda (indy) and sta (indy) device structure cmos package 80p6n operating temperature range -20 to 85 o c
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification mcu features 6/2/98 1-5 1.1 mcu features ? 7600 8-bit cpu core, cmos process ? minimum instruction execution time of 83ns (1-cycle instruction @ f = 12 mhz) ? ef?cient software support (c and/or assembly) ? rom: 32 kb on-chip ? ram: 1 kb on-chip ? built-in microprocessor or memory-expansion modes ? three slow memory wait modes: software wait, rdy wait, and extended rdy wait ? nine i/o ports, total 66 programmable i/o pins available ? programmable direction control on every i/o pin ? software selectable slew rate control on every i/o pin ? master cpu bus interface: ? mcu can be operated in slave mode by control signals from the host cpu ? 8 data lines (dq7-dq0) and r(e), w(r/ w), a 0 , s 0 , s 1 , ibf 0 , obf 0 , ibf 1 , obf 1 signals available ? master cpu sends and receives data, command, and status by means of dq7-dq0 ? usb function control unit ? usb transceiver (conforms to usb v1.0 speci?cation) ? dma controller: ? two dma channels available ? 16 address lines for 64k byte address space ? single byte or burst transfer modes ? transfer request by external pins, software triggers or built-in peripherals ? maximum 6m byte/sec transfer speed (in burst mode) ? timers: three 8-bit timers and two 16-bit timers available ? two full duplex uarts available ? one master/slave clock synchronous i/o (sio), internal or external clock selectable ? built-in special count source generator (scsg): can be a clock source for timer x, uarts, and sio ? power-saving wait (idle) and stop (powerdown) modes.
1-6 6/2/98 pin description and layout 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 1.2 pin description and layout figure 1-2. pin layout p3 0 /[rdy] p7 4 /obf 1 p4 0 /[ edma] 41 40 24 65 p7 3 / ibf 1 / hld a66 p7 2 / s1 67 p7 1 /( hold) 68 p7 0 /( sof) 69 usb d+ 70 usb d- 71 ext. cap 72 v ss 73 v cc 74 p6 7 /dq7 75 p6 6 /dq6 76 p6 5 /dq5 77 p6 4 /dq4 78 p6 3 /dq3 79 p6 2 /dq2 80 p4 1 /int0 23 p4 2 /int1 22 p4 3 /cntr0 21 p4 4 /cntr1 20 lpf 19 av ss 18 av cc 17 v cc 16 x out 15 x in 14 v ss 13 p5 0 /xc in 12 p5 1 /t out /xc out 11 reset 10 cnv ss 9 p5 2 /obf 0 8 p5 3 / ibf 0 7 p5 4 / s 0 6 p5 5 /a 0 5 p5 6 / r(e) 4 p5 7 / w(r/ w) 3 p6 0 /dq0 2 p6 1 /dq1 1 p3 1 39 p3 2 38 p3 3 /[dma out ] 37 p3 4 /[ f out ] 36 p3 5 /[sync out ] 35 p3 6 /[ wr] 34 p3 7 /[ rd] 33 p8 0 /utxd2/ srd y 32 p8 1 /urxd2/sclk 31 p8 2 / cts2/srxd 30 p8 3 / rts2/stxd 29 p8 4 /utxd1 28 p8 5 /urxd1 27 p8 6 / cts1 26 p8 7 / rts1 25 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p1 7 /[ab15] p1 6 /[ab14] p1 5 /[ab13] p1 4 /[ab12] p1 3 /[ab11] p1 2 /[ab10] p1 1 /[ab9] p1 0 /[ab8] p0 7 /[ab7] p0 6 /[ab6] p0 5 /[ab5] p0 4 /[ab4] p0 3 /[ab3] p0 2 /[ab2] p0 1 /[ab1] p0 0 /[ab0] p2 7 /[db7] p2 6 /[db6] p2 5 /[db5] p2 4 /[db4] p2 3 /[db3] p2 2 /[db2] p2 1 /[db1] p2 0 /[db0] M37640E8-XXXFP [ ]indicates function in memory expansion and microprocessor modes
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification pin description and layout 6/2/98 1-7 table 1-2. pin description name i/o description pin # p0 0 /ab0 ~ p1 7 /ab15 i/o cmos i/o port (address bus). when the mcu is in memory expansion or microprocessor mode, these pins function as the address bus. 56-41 p2 0 /db0 ~ p2 7 /db7 i/o cmos i/o port (data bus). when the mcu is in memory expansion or microprocessor mode, these pins function as the data bus. these pins may also be used to implement the key-on wake up function. 64-57 p3 0 /rdy i/o cmos i/o port (ready). when the mcu is in memory expansion or microprocessor mode, this pin functions as rdy (hardware wait cycle control). 40 p3 1 i/o cmos i/o port. 39 p3 2 /(vrfy) i/o cmos i/o port. when the mcu is in eprom program mode, the pin is used as vrfy (eprom memory verify). 38 p3 3 /dma out / pgm i/o cmos i/o port (dma out ). when the mcu is in memory expansion or microprocessor mode, this pin is set to a 1 during a dma transfer. when the mcu is in eprom program mode, the pin is used as pgm (eprom memory program). 37 p3 4 / f out i/o cmos i/o port ( f ). when the mcu is in memory expansion or microprocessor mode, this pin becomes f out pin. 36 p3 5 /sync out i/o cmos i/o port (sync output). when the mcu is in memory expansion or microprocessor mode, this pin becomes the syncout pin. 35 p3 6 / wr/( ce) i/o cmos i/o port. ( wr output). when the mcu is in memory expansion or microprocessor mode, this pin becomes wr. when the mcu is in eprom program mode, the pin is used as ce (eprom memory chip enable). 34 p3 7 / rd/( oe) i/o cmos i/o port. ( rd output). when the mcu is in memory expansion or microprocessor mode, this pin becomes rd. when the mcu is in eprom program mode, the pin is used as oe (eprom memory output enable). 33 p4 0 / edma i/o cmos i/o port ( edma: expanded data memory access). when the mcu is in memory expansion or microprocessor mode, this pin can become the edma pin. 24 p4 1 /int0 ~ p4 2 /int1 i/o cmos i/o port or external interrupt ports int0 and int1. these external interrupts can be con?gured to be active high or low. 23-22 p4 3 /cntr0 i/o cmos i/o port or timer x input pin for pulse width measurement mode and event counter mode or timer x output pin for pulse output mode. this pin can also be used as an external interrupt when timer x is not in output mode. the interrupt polarity is selected in the timer x mode register. 21 p4 4 /cntr1 i/o cmos i/o port or timer y input pin for pulse period measurement mode, pulse h-l measurement mode and event counter mode or timer y output pin for pulse output mode. this pin can also be used as an external interrupt when timer y is not in output mode. the interrupt polarity is selected in the timer y mode register. 20 p5 0 /xc in i/o cmos i/o port or xc in . 12 p5 1 /t out / xc out i/o cmos i/o port or timer 1/2 pulse output pin (can be con?gured initially high or initially low), or xc out .11 p5 2 /obf 0 i/o cmos i/o port or obf 0 output to master cpu for data bus buffer 0. 8 p5 3 / ibf 0 i/o cmos i/o port or ibf 0 output to master cpu for data bus buffer 0. 7 p5 4 / s 0 i/o cmos i/o port or s 0 input from master cpu for data bus buffer 0. 6 p5 5 /a 0 i/o cmos i/o port or a 0 input from master cpu. 5 p5 6 / r(e) i/o cmos i/o port or r(e) input from master cpu. 4 p5 7 / w(r/ w) i/o cmos i/o port or w(r/ w) input from master cpu. 3 p6 0 /dq0 ~ p6 7 /dq7 i/o cmos i/o port or master cpu data bus. 2-1, 80-75 usb d - i/o usb d- voltage line interface, a series resistor of 33 w should be connected to this pin. (see note) 71 usb d + i/o usb d+ voltage line interface, a series resistor of 33 w should be connected to this pin. (see note) 70 p7 0 / sof i/o cmos i/o port or usb start of frame pulse output, an 80 ns pulse outputs on this pin for every usb frame. 69 p7 1 / hold i/o cmos i/o port or hold pin. 68 p7 2 / s 1 i/o cmos i/o port or s 1 input from master cpu for data bus buffer 1. 67
1-8 6/2/98 pin description and layout 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers d+/d- line driver notes: in order to match the usb cable impedance, a series resistor of 33w, 1%, 1/8 w should be connected to each usb line; i.e. on d+ (pin 70) and on d- (pin 71). also, a coupling capacitor with the recommended value of 33pf should be connected between d+ and d- after the 33 w series resistors. if the usb line is improperly terminated or not matched, signal fidelity will suffer, resulting in excessive overshoot or undershoot. this will potentially introduce bit errors. vdd/vss notes: in order to reduce the effects of the inductance of the traces on the board, decoupling capacitors should be connected between pins 73(vss) and 74(vdd), 13(vss) and 16(vdd), and 17(avdd) and 19(avss). recommended values are a 4.7 m f in parallel with a 0.1 m f. figure 1-3. vdd/vss decoupling capacitor connections p7 3 / ibf 1 / hld a i/o cmos i/o port or ibf 1 output to master cpu for data bus buffer 1, or hld a pin. ibf 1 and hld a are mutually exclusive. ibf 1 has priority over hld a. 66 p7 4 /obf 1 i/o cmos i/o port or obf 1 output to master cpu for data bus buffer 1. 65 p8 0 /utxd2/ srd y i/o cmos i/o port or uart2 pin utxd2 or sio pin srd y. uart2 and sio are mutually exclusive, uart2 has priority over sio. 32 p8 1 /urxd2/ sclk i/o cmos i/o port or uart2 pin urxd2 or sio pin sclk. uart2 and sio are mutually exclusive, uart2 has priority over sio. 31 p8 2 / cts2/ srxd i/o cmos i/o port or uart2 pin cts2 or sio pin srxd. uart2 and sio are mutually exclusive, uart2 has priority over sio. 30 p8 3 / rts2/ stxd i/o cmos i/o port or uart2 pin r ts2 or sio pin stxd. uart2 and sio are mutually exclusive, uart2 has priority over sio. 29 p8 4 /utxd1 i/o cmos i/o port or uart1 pin utxd1. 28 p8 5 /urxd1 i/o cmos i/o port or uart1 pin urxd1. 27 p8 6/ cts1 i/o cmos i/o port or uart1 pin cts1. 26 p8 7 / rts1 i/o cmos i/o port or uart1 pin rts1. 25 av cc ,av ss i power supply inputs for analog circuitry av cc = 4.15~ 5.25v, av ss = 0v 17,19 cnv ss i controls the processor mode of the chip. normally connected to v ss or v cc . when the mcu is in eprom program mode, this pin supplies the programming voltage to the eprom. 9 v cc ,v ss i power supply inputs: v cc = 4.15~ 5.25v, v ss = 0v 16/74, 13/73 reset i to enter the reset state, this pin must be kept l for more that 2 m s (20 f cycles under normal v cc conditions). if the crystal or ceramic resonator requires more time to stabilize, extend this l level time appropriately. 10 xc in xc out i o an external ceramic or quartz crystal oscillator can be connected between the xc in and xc out pins. if an external clock source is used, connect the clock source to the xc in pin and leave the xc out pin open. 12 11 x in x out i o input and output signals to and from the internal clock generation circuit. connect a ceramic resonator or quartz crystal between x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 14 15 lpf o loop ?lter for the frequency synthesizer. 18 ext. cap i an external capacitor (ext. cap) pin. when the usb transceiver voltage converter is used, a 2 m f or larger capacitor should connect between this pin and v ss to ensure proper operation of the usb line driver. the voltage converter is enabled by setting bit 4 of the usb control register (0013 16 ) to a 1. 72 table 1-2. pin description name i/o description pin # c1 c2 pin 73 pin 74 ( vdd ) ( vss ) c1 c2 pin 13 pin 16 ( vdd ) ( vss ) c1 c2 pin 17 pin 19 (a vdd ) (a vss ) c1 = 4.7 m f c2 = 0.1 m f
mitsubishi semiconductor america, inc. preliminary chapter 2 functional description 2.1 central processing unit . . . . . . 2-3 2.2 cpu mode registers . . . . . . . . 2-7 2.3 oscillator circuit . . . . . . . . . . . . 2-8 2.4 memory map . . . . . . . . . . . . . . 2-14 2.5 processor modes . . . . . . . . . . 2-17 2.6 peripheral interface . . . . . . . . . 2-25 2.7 input and output ports . . . . . . 2-28 2.8 interrupt control unit . . . . . . . 2-43 2.9 universal serial bus . . . . . . . . 2-49 2.10 master cpu bus interface . . 2-65 2.11 direct memory access controller . . . . . . . . . . . . . 2-69 2.12 special count source generator . . . . . . . . . . . . . 2-79 2.13 timers . . . . . . . . . . . . . . . . . . 2-82 2.14 uart . . . . . . . . . . . . . . . . . . . 2-90 2.15 serial i/o . . . . . . . . . . . . . . . 2-102 2.16 low power modes . . . . . . . 2-105 2.17 reset . . . . . . . . . . . . . . . . . . 2-107 2.18 key-on wake-up . . . . . . . . 2-108
2-2 7/9/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification central processing unit 7/9/98 2-3 2 functional description 2.1 central processing unit the central processing unit (cpu) has six registers: ? accumulator (a) ? index register x (x) ? index register y (y) ? stack pointer (s) ? processor status register (ps) ? program counter (pc) 2.1.1 register structure figure 2-1. register structure five of the cpu registers are 8-bit registers. these are the accumulator (a), index register x (x), index register y (y), stack pointer (s), and the processor status register (ps). the program counter (pc) is a 16-bit register consisting of two 8-bit registers (pch and pcl) (see figure 2-1.). after a hardware reset, bit 2 (the i flag) of the ps is set high and the values at the addresses fffa 16 and fffb 16 are stored in the pc, but the values of the other bits of the ps and the other registers are undefined. initialization of undefined registers may be necessary for some programs. 2.1.2 accumulator (a) the accumulator is the main register of the microcomputer. data operations such as data transfer, input/ output, and so forth, are executed mainly through the accumulator. 0 7 accumulator 0 7 index register x 0 7 index register y 0 7 stack pointer 0 7 pc l 15 pc h 0 7 carry flag (bit 0) zero flag (bit 1) interrupt disable flag (bit 2) decimal mode flag (bit 3) break flag (bit 4) index x mode flag (bit 5) over?ow flag (bit 6) negative flag (bit 7) program counter d i z c n v t b processor status register
2-4 7/9/98 central processing unit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.1.3 index registers x and y both index registers x and y are 8-bit registers. in the absolute addressing modes, the contents of these registers are added to the value of the operand to specify the real address. in the indirect x addressing mode, the value of the operand is added to the contents of register x to specify the zero page basic address. the data at the basic address specifies the real address. in the indirect y addressing mode, the value of the operand specifies a zero page address. the data at this address is added to the contents of register y to produce the real address. these addressing modes are useful for referencing subroutine tables and memory tables. when the t ?ag in the processor status register is set high, the value contained in index register x points to a zero page memory location that replaces the accumulator for most accumulator based instructions. 2.1.4 stack pointer the stack pointer is an 8-bit register used during subroutine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. the lower eight bits of the stack address are determined by the contents of the stack pointer. the upper eight bits of the stack address are determined by the stack page select bit, bit 2 of the cpu mode register a. if the stack page select bit is 0, then the ram in the zero page (addresses 0070 16 to 00ff 16 ) is used as the stack area. if the stack page select bit is 1 (the default value), then the ram in one page (addresses 0100 16 to 01ff 16 ) is used as the stack area. the base of the stack must be set in software, and stack grows towards lower addresses from that point. the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 2-2. 2.1.5 program counter the program counter (pc) is a 16-bit register consisting of two 8-bit sub-registers pch and pcl. it is used to indicate the address of the next instruction to be executed.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification central processing unit 7/9/98 2-5 figure 2-2. register push and pop when servicing interrupts and calling subroutines note 1. the condition to enable an interrupt: interrupt enable bit is set to a 1 and interrupt inhibit ?ag (i ?ag) is a 0. note 2. when an interrupt occurs, the address of the next instruction to be executed is stored on the stack. when a subroutine is called, the address of (next instruction -1) to be executed is stored on the stack. 2.1.6 processor status register the processor status (ps) register is an 8-bit register consisting of flags that indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c), zero (z), overflow (v), or the negative (n) flags. after reset, the i flag is set to a 1, but all other flags are undefined. because the t and d flags directly affect arithmetic operations, they should be initialized in the beginning of a program. carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it is also affected by shift and rotate instructions. the c flag can be set directly by the set carry (sec) instruction and cleared by the clear carry (clc) instruction. main routine . . . . . . . . . . . . . . execute jsr m(s) (pch) (s) (s-1) m(s) (pcl) (s) (s-1) subroutine execute rts (s) (s+1) (pcl) m(s) (s) (s+1) (pch) m(s) (pc) (pc+1) m(s) (ps) (s) (s-1) interrupt routine execute rti (s) (s+1) (ps) m(s) interrupt request (note 1) return address stored on stack (note 2) return address restored contents of processor status register restored on stack contents of processor status register restored i flag set high jump vector fetched return address stored on stack (note 2) return address restored m(s) (pch) (s) (s-1) m(s) (pcl) (s) (s-1) (s) (s+1) (pcl) m(s) (s) (s+1) (pch) m(s) . . . . . . .
2-6 7/9/98 central processing unit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers zero flag (z) the z flag is set if the result of an arithmetic operation or a data transfer is 0, and cleared if the result is anything other than 0. interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction and any non-maskable interrupts, if available. interrupts are disabled when the i flag is 1. when an interrupt occurs, this flag is automatically set to a 1 to prevent other interrupts from interfering until the current interrupt service routine is completed. the i flag can be set by the set interrupt disable (sei) instruction and cleared by the clear interrupt disable (cli) instruction. decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0; decimal arithmetic is executed when it is 1. decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. the d flag can be set by the set decimal mode (sed) instruction and cleared by the clear decimal mode (cld) instruction. break flag (b) the b flag is used to indicate whether the current interrupt was generated by the brk instruction. the brk flag in the processor status register is nominally 0. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to a 1. the saved processor status is the only place where the break flag is ever set. index x mode flag (t) when the t flag is 0, arithmetic operations are performed between accumulator and memory, and the results are stored in the accumulator. when the t flag is 1, direct arithmetic operations and direct data transfers are enabled between memory and memory, as well as between i/o and i/o. the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal addressing modes. the t flag can be set by the set t flag (set) instruction and cleared by the clear t flag (clt) instruction. because the t flag directly affects calculations, it should be initialized after a reset. over?ow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds the range from +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. the v flag can be cleared by the clv instruction, but there is no set instruction. in decimal mode, the v flag is invalid. negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative, that is (bit 7 is 1). when the bit instruction is executed, bit 7 of the memory location operated by the bit instruction is stored in the negative flag. there are no instructions for directly setting or clearing the n flag.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification cpu mode registers 7/9/98 2-7 2.2 cpu mode registers this device has two cpu mode registers: cpu mode register a (cpma) and cpu mode register b (cpmb) that control the processor mode, clock, slow memory wait and other cpu functions. the bit representation of each register is described in figure 2-3 and figure 2-4: figure 2-3. cpu mode register a figure 2-4. cpu mode register b address description acronym and value at reset 0000 16 cpu mode register a cpma=0c 0001 16 cpu mode register b cpmb=83 cpma0,1 processor mode bits (bits 1,0) bit 1 bit 0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: not used cpma2 stack page selection bit (bit 2) 0: in page 0 area 1: in page 1 area cpma3 x cout drive capacity selection bit (bit 3) 0: low 1: high cpma4 clock xc in -xc out stop bit (bit 4) 0: stop 1: oscillator cpma5 clock x in -x out stop bit (bit 5) 0: oscillator 1: stop cpma6 internal clock selection bit (bit 6) 0: external clock 1: f syn cpma7 external clock selection bit (bit 7) 0: x in -x out 1: xc in -xc out msb 7 lsb 0 cpma7 cpma6 cpma5 cpma4 cpma3 cpma2 cpma1 cpma0 access: r/w reset: 0c 16 address: 0000 16 cpmb0,1 slow memory wait bits (bits 1,0) bit 1 bit 0 0 0: no wait 0 1: one time wait 1 0: two time wait 1 1: three time wait cpmb2,3 slow memory mode bit (bits 3,2) bit 3 bit 2 0 0: software wait 0 1: not used 1 0: fixed wait by rdy pin l 1 1: extended rdy wait cpmb4 expanded data memory access bit (bit 4) 0: edma output disabled (64 kbyte data access area) 1: edma output enabled (greater than 64 kbytes data access area) cpmb5 hold function enable bit (bit 5) 0: hold function disabled 1: hold function enabled cpmb6 reserved (read/write 0) cpmb7 x out drive capacity selection bit (bit 7) 0: low 1: high (default state after reset and after stop mode) access: r/w reset: 83 16 address: 0001 16 msb 7 lsb 0 cpmb4 cpmb3 cpmb2 cpmb1 cpmb0 cpmb7 reserved cpmb5
2-8 7/9/98 oscillator circuit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.3 oscillator circuit 2.3.1 description an on-chip oscillator provides the system and peripheral clocks as well as the usb clock necessary for operation. this oscillator circuit is comprised of amplifiers that provide the gain necessary for oscillation, oscillation control logic, a frequency synthesizer, and buffering of the clock signals. a flow diagram for the oscillator circuit is shown in figure 2-6 and a block diagram of the oscillator circuit is shown in figure 2-7. the following external clock inputs are supported: ? a quartz crystal oscillator of up to 24 mhz, connected to the x in and x out pins. ? an external clock signal of up to 48 mhz, connected to the x in pin. ? a ceramic resonator or quartz crystal oscillator of 32.768 khz, connected to the xc in and xc out pins. ? an external clock signal of up to 5.12 mhz, connected to the xc in pin. the frequency synthesizer can be used to generate a 48mhz clock signal (f usb ) needed by the usb block and clock f syn , which can be chosen as the source for the system and peripheral clocks. both f usb and f syn are phase-locked frequency multiples of the frequency synthesizer input. the inputs to the frequency synthesizer can be either x in or xc in . the two-phase non-overlapping system clock (cpu and peripherals) is derived from the source to the clock circuit and is 1/2 the frequency of the source. (i.e. source = 24 mhz, system clock = 12 mhz) any one of four clock signals can be chosen as the source for the system and peripheral clocks; f xin / 2, f xin , f xcin , or f syn . the selection is based on the values of bits cpma6, cpma7 and ccr7. the default source after reset is f xin /2. the default source for the system and peripheral clocks is f xin /2. if f xin = 24mhz, then the cpu will be running at f = 6mhz (low frequency mode. for the cpu to run in high frequency mode, i.e., source of clock = f xin , write a 1 to bit 7 of the clock control register. figure 2-5. clock control register the drive strength of the x out and xc out inverting amplifier can be controlled by bits cpmb7 and cpma3, respectively. high drive is the default at reset or after executing a stp instruction and must be chosen whenever restarting x in or xc in oscillation if a ceramic or crystal oscillator is used. when oscillation has been established, low drive can be selected to reduce power consumption. if an external clock signal is input to x in or xc in , the inverting amplifiers can be disabled by means of the ccr6 and ccr7 bits, respectively, in order to reduce power consumption. bits 0-3 reserved (read/write 0) ccr4: pll bypass bit (bit 4) 0: f usb = f vco (frequency synthesizer output) 1: f usb = f xin ccr5: xc out oscillation drive disable bit (bit 5) 0: xc out oscillation drive is enabled (when xc in oscillation is enabled). 1: xc out oscillation drive is disabled. ccr6: x out oscillation drive disable bit (bit 6) 0: x out oscillation drive is enabled (when x in oscillation is enabled). 1: x out oscillation drive is disabled. ccr7: x in divider select bit (bit 7) 0: f xin /2 is used for the system clock source when cmpa7:6=00 1: f xin is used for the system clock source when cmpa7:6=00 msb 7 lsb 0 reserved reserved reserved access: r/w reset: 00 16 reserved address: 001f 16 ccr4 ccr7 ccr6 ccr5
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification oscillator circuit 7/9/98 2-9 figure 2-6. clock flow diagram xin clock stopped xcin clock on pll clock stopped f =f(xcin)/2 cpma=bc, fsc=68 xin clock stopped xcin clock on pll clock on note 3 f =f(xcin)/2 cpma7=bc, fsc=49 xin clock stopped xcin clock on pll clock on f =f(pll)/2 cpma7=fc, fsc=49 xin clock on xcin clock on pll clock on f =f(pll)/2 cpma=dc, fsc=41 xin clock on xcin clock on pll clock on note 3 f =f(xcin)/2 cpma=9c, fsc=41 xin clock on xcin clock on pll clock stopped f =f(xcin)/2 cpma=9c, fsc=60 xin clock on xcin clock on pll clock stopped f =f(xin)/4 note 2 cpma=1c, fsc=60 xin clock on xcin clock on pll clock on note 3 f =f(xin)/4 note 2 cpma=1c, fsc=41 xin clock on xcin clock on pll clock on f =f(pll)/2 cpma=5c, fsc=41 xin clock on xcin clock stopped pll clock on f =f(pll)/2 cpma=4c, fsc=41 stop note 1 wait stop note 1 wait stop note 1 wait stop note 1 wait wait wait wait wait reset fsc0 cpma6 10 cpma4 cpma7 cpma5 note 4 10 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 fsc0 fsc0 fsc0 cpma6 cpma6 cpma6 note: cpma values shown assume single-chip mode with stack in one page. xin clock on xcin clock stopped pll clock stopped f =f(xin)/4 note 2 cpma=0c, fsc=60 xin clock on xcin clock stopped pll clock on note 3 f =f(xin)/4 note 2 cpma=0c, fsc=41 note 1: stop mode stops the oscillators which are also the inputs to the frequency synthesizer. note 2 : f =f(x in )/4 can be inter-changed with f =f(x in )/2 by setting ccr7 to 1. the same ?ow-chart applies for both cases. however, the frequency synthesizer is not disabled and so its output is unstable. so, always set the system clock to an external oscillator and disable the frequency synthesizer before note 3: the input to the frequency synthesizer is independent of the system clock. it can be either x in or xc in depending on bit 3 of fsc. in the above ?ow, the input has been chosen to be the same as the system clock only for simplicity. the oscillator selected to be the input to the frequency synthesizer must be enabled before the frequency synthesizer is enabled. entering stop mode. note 4 : the input clock for the frequency synthesizer must be set to xcin by setting fin (bit 3 of fsc) to a 1 before xin oscillation can be disabled.
2-10 7/9/98 oscillator circuit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-7. clock block diagram xoscstp d q t r pin1 d q t r r q s d q t d q t p2+ stp oscillator countdown timer 1->2 p2 peripheral p1 peripheral pin1 p2+ resetb r q s r q s d q t r q s d q t d q t s q r f out p2 peripheral p1 peripheral p2 out p1 out p2+ pin2 stp slow memory wait p1+,p2+ rdy cpmb0 cpmb1 cpmb2 cpmb3 frequency synthesizer enable fsc0 cpma6 pin1,pin2 cpma7 f in f syn cpma5 oscstp delay stp padresetb i flag interrupt request x in x out f xin xc in xc out 1/2 usb 48mhz clock cpma3 cpmb7 cpma4 xoscstp xcoscstp cpma5 cpma4 s r qb xcoscstp lpf f xcin lpf xcdoscstp xcod xdoscstp xod stp wit d q t r pin1 d q t r pin2 padresetb p1hatrstb p2latrstb p2latrstb p1hatrstb p2 p1 p2latrstb p1hatrstb lpf fin(fsc3) f ext 1/2 ccr4 ccr7
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification oscillator circuit 7/9/98 2-11 2.3.2 frequency synthesizer circuit the frequency synthesizer circuit generates a 48mhz clock needed by the usb block and a clock f syn that are both a multiple of the external input reference clock f in . a block diagram of the circuit is shown in figure 2-8. figure 2-8. frequency synthesizer circuit the frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro, and four registers, namely fsm1, fsm2, fsc and fsd. two multiply registers (fsm1, fsm2) control the frequency multiply amount. clock f in is prescaled using fsm2 to generate f pin . f pin is multiplied using fsm1 to generate an f vco clock which is then divided using fsd to produce the clock f syn . the f vco clock is optimized for 48 mhz operation and is buffered and sent out of the frequency synthesizer block as signal f usb . this signal is used by the usb block. clock f pin is a divided down version of clock f in , which can be either f xin or f xcin . the default clock after reset is f xin . the relationship between f pin and the clock input to the prescaler (f in ) is as follows: ?f pin = f in / 2(n+1) where n is a decimal number between 0 and 254. setting fsm2 to 255 disables the prescaler and f pin = f in . figure 2-9. frequency synthesizer multiply control register fsm2 data bus fsm2 fsm1 fsc fsd 006e 006d 006c 006f frequency multiplier frequency divider 8 bit ls 8 bit f in f vco f syn f usb prescaler 8 bit f pin f in /2( n +1) = f pin f pin fsm2 f in dec(n) hex(n) 24 mhz 255 ff 24.00 mhz 1 mhz 11 0c 24.00 mhz 2 mhz 5 05 24.00 mhz 3 mhz 3 03 24.00 mhz 6 mhz 1 01 24.00 mhz 12 mhz 0 00 24.00 mhz msb 7 lsb 0 bit 6 bit 1 bit 0 bit 2 bit 5 bit 4 bit 3 bit 7 access: r/w address: 006e 16 reset: ff 16
2-12 7/9/98 oscillator circuit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-10. frequency synthesizer multiply control register fsm1 figure 2-11. frequency synthesizer divide register the relationship between f pin , f vco , and f syn is as follows: ?f vco = f pin x 2( n +1) where n is the decimal equivalent of the value loaded in fsm2, fsm1. note: n must be chosen such that f vco equals 48 mhz. ?f syn = f vco / 2(m+1) where m is the decimal equivalent of the value loaded in fsd note: setting m = 255 disables the divider and disables f syn . the fsc0 bit in the fsc control register enables the frequency synthesizer block. when disabled (fsc0 = 0), f vco is held at either a high or low state. when the frequency synthesizer control bit is active (fsc0 = 1), a lock status (ls = 1) indicates that f syn and f vco are the correct frequency. the ls and fsco control bits in the fsc control register are shown in figure 2-12. when using the frequency synthesizer, a low-pass filter must be connected to the lpf pin. once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the frequency synthesizer is used. this is done to allow the output to stabilize. it is also recommended that none of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be temporarily (2-5ms) unstable. f vco /2( n +1) = f pin f pin fsm1 f vco dec(n) hex(n) 320 khz 74 4a 48.00 mhz 2 mhz 11 0b 48.00 mhz 4 mhz 5 05 48.00 mhz 6 mhz 3 03 48.00 mhz 12 mhz 1 01 48.00 mhz 24 mhz 0 00 48.00 mhz msb 7 lsb 0 bit 6 bit 1 bit 0 bit 2 bit 5 bit 4 bit 3 bit 7 address: 006d 16 access: r/w reset: ff 16 f vco /2(m+1) = f syn f vco fsd f syn dec(m) hex(m) 48.00 mhz 00 00 24.00 mhz 48.00 mhz 127 7f 187.50 khz msb 7 lsb 0 bit 6 bit 1 bit 0 address: 006f 16 access: r/w reset: ff 16 bit 2 bit 5 bit 4 bit 3 bit 7
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification oscillator circuit 7/9/98 2-13 figure 2-12. frequency synthesizer control register fse frequency synthesizer enable bit (bit 0) 0: disabled 1: enabled vco1,0 vco gain control (bits 2,1) bit 2 bit 1 0 0: lowest gain (recommended) 0 1: low gain 1 0: high gain 1 1: highest gain fin frequency synthesizer input selector bit (bit 3) 0: x in 1: xc in bit 4 reserved (read/write 0) chg1,0 lpf current control (bits 6,5) bit 6 bit 5 0 0: disabled 0 1: low current 1 0: intermediate current (recommended) 1 1: high current ls frequency synthesizer lock status bit (bit 7) (read only; write 0) 0: unlocked 1: locked msb 7 lsb 0 chg0 fin vco0 fse address: 006c 16 access: r/w reset: 60 16 vco1 ls chg1 reserved
2-14 7/9/98 memory map 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.4 memory map figure 2-13. memory map the first 112 bytes of memory from 0000 16 to 006f 16 is the special function register (sfr) area and contains the cpu mode registers, interrupt registers, and other registers to control peripheral functions (see figure 2-13.). the general purpose ram resides from 0070 16 to 046f 16 . when the mcu is in memory expansion or microprocessor mode and external memory is overlaid on the internal ram, the cpu reads data from the internal ram. however, the cpu writes data in both the internal and external memory. the area from 0470 16 to 7fff 16 is not used in single-chip mode, but can be mapped for an external memory device when the mcu is in memory expansion or microprocessor mode. the area from 8000 16 to 807f 16 and from fffc 16 to ffff 16 are factory reserved areas. mitsubishi uses it for test and evaluation purposes. the user can not use this area in single-chip or memory expansion modes. the user 32k byte rom resides from 8080 16 to fffb 16 . when the mcu is in microprocessor mode, the cpu accesses an external area rather than accessing the internal rom. zero page and special page area can be accessed by 2-byte commands by using special addressing modes. sfr area reserved area zero page special page for subroutine calls not used reserved area 0000 16 006f 16 0070 16 00ff 16 0100 16 046f 16 0470 16 7fff 16 8000 16 807f 16 8080 16 feff 16 ff00 16 ffc9 16 ffca 16 fffb 16 fffc 16 ffff 16 ram 1k bytes rom 32k bytes
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification memory map 7/9/98 2-15 2.4.1 zero page the 256 bytes zero page area is where the sfr and part of the internal ram are allocated. the zero page addressing modes can be used to specify memory and register addresses in this area (see figure 2-14.). these dedicated addressing modes enable access to this area with fewer instruction cycles. figure 2-14. zero page and special page addressing modes 2.4.2 special page the 256 bytes from address ff00 16 to ffff 16 are called the special page area. in this area special page addressing can be used to specify memory addresses (see figure 2-14.). this dedicated special page addressing mode enables access to this area with fewer instruction cycles. frequently used subroutines are normally stored in this area. 2.4.3 special function registers the special function registers (sfr) are used for controlling the functional blocks, such as i/o ports, timers, uart, and so forth (see table 2-1.). the reserved addresses should not be read or written to. zero page (2 byte instruction) zero page indirect (2 byte instruction) zero page x (2 byte instruction) zero page y (2 byte instruction) zero page bit (2 byte instruction) zero page bit relative (3 byte instruction) absolute (3 byte instruction) absolute x (3 byte instruction) absolute y (3 byte instruction) relative (2 byte instruction) indirect (3 byte instruction) indirect x (2 byte instruction) indirect y (2 byte instruction) special page (2 byte instruction) addressing modes for zero page only addressing modes in which zero page access is possible addressing modes in which special page access is possible addressing mode for special page only
2-16 7/9/98 memory map 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers table 2-1. sfr addresses addr description acronym and value at reset addr description acronym and value at reset 0000 16 cpu mode register a cpma=0c 0038 16 uart2 mode register u2mod=00 0001 16 cpu mode register b cpmb=03 0039 16 uart2 baud rate generator u2brg=xx 0002 16 interrupt request register a ireqa=00 003a 16 uart2 status register u2sts=03 0003 16 interrupt request register b ireqb=00 003b 16 uart2 control register u2con=00 0004 16 interrupt request register c ireqc=00 003c 16 uart2 transmit/receiver buffer 1 u2trb1=xx 0005 16 interrupt control register a icona=00 003d 16 uart2 transmit/receiver buffer 2 u2trb2=xx 0006 16 interrupt control register b iconb=00 003e 16 uart2 rts control register u2rtsc=80 0007 16 interrupt control register c iconc=00 003f 16 dmac index and status register dmais=00 0008 16 port p0 p0=00 0040 16 dmac channel x mode register 1 dmaxm1=00 0009 16 port p0 direction register p0d=00 0041 16 dmac channel x mode register 2 dmaxm2=00 000a 16 port p1 p1=00 0042 16 dmac channel x source register low dmaxsl=00 000b 16 port p1 direction register p1d=00 0043 16 dmac channel x source register high dmaxsh=00 000c 16 port p2 p2=00 0044 16 dmac channel x destination register low dmaxdl=00 000d 16 port p2 direction register p2d=00 0045 16 dmac channel x destination register high dmaxdh=00 000e 16 port p3 p3=00 0046 16 dmac channel x count register low dmaxcl=00 000f 16 port p3 direction register p3d=00 0047 16 dmac channel x count register high dmaxch=00 0010 16 port control register ptc=00 0048 16 data bus buffer register 0 dbb0=00 0011 16 interrupt polarity selection register ipol=00 0049 16 data bus buffer status register 0 dbbs0=00 0012 16 port p2 pull-up control register pup2=00 004a 16 data bus buffer control register 0 dbbc0=00 0013 16 usb control register usbc=00 004b 16 reserved 0014 16 port p6 p6=00 004c 16 data bus buffer register 1 dbb1=00 0015 16 port p6 direction register p6d=00 004d 16 data bus buffer status register 1 dbbs1=00 0016 16 port p5 p5=00 004e 16 data bus buffer control register 1 dbbc1=00 0017 16 port p5 direction register p5d=00 004f 16 reserved 0018 16 port p4 p4=00 0050 16 usb address register usba=00 0019 16 port p4 direction register p4d=00 0051 16 usb power management register usbpm=00 001a 16 port p7 p7=00 0052 16 usb interrupt status register 1 usbis1=00 001b 16 port p7 direction register p7d=00 0053 16 usb interrupt status register 2 usbis2=00 001c 16 port p8 p8=00 0054 16 usb interrupt enable register 1 usbie1=00 001d 16 port p8 direction register p8d=00 0055 16 usb interrupt enable register 2 usbie2=00 001e 16 reserved 0056 16 usb frame number register low usbsofl=00 001f 16 clock control register ccr=00 0057 16 usb frame number register high usbsofh=00 0020 16 timer xl txl=ff 0058 16 usb endpoint index usbindex=00 0021 16 timer xh txh=ff 0059 16 usb endpoint x in csr in_csr=00 0022 16 timer yl tyl=ff 005a 16 usb endpoint x out csr out_csr=00 0023 16 timer yh tyh=ff 005b 16 usb endpoint x in maxp in_maxp=00 0024 16 timer 1 t1=ff 005c 16 usb endpoint x out maxp out_maxp=00 0025 16 timer 2 t2=01 005d 16 usb endpoint x out wrt_cnt low wrt_cntl=00 0026 16 timer 3 t3=ff 005e 16 usb endpoint x out wrt_cnt high wrt_cnth=00 0027 16 timer x mode register txm=00 005f 16 reserved 0028 16 timer y mode register tym=00 0060 16 usb endpoint 0 fifo usbfifo0=n/a 0029 16 timer 123 mode register t123m=00 0061 16 usb endpoint 1 fifo usbfifo1=n/a 002a 16 sio shift register siosht=xx 0062 16 usb endpoint 2 fifo usbfifo2=n/a 002b 16 sio control register 1 siocon1=00 0063 16 usb endpoint 3 fifo usbfifo3=n/a 002c 16 sio control register 2 siocon2=18 0064 16 usb endpoint 4 fifo usbfifo4=n/a 002d 16 special count source generator1 scsg1=ff 0065 16 reserved 002e 16 special count source generator2 scsg2=ff 0066 16 reserved 002f 16 special count source mode register scsm=00 0067 16 reserved 0030 16 uart1 mode register u1mod=00 0068 16 reserved 0031 16 uart1 baud rate generator u1brg=xx 0069 16 reserved 0032 16 uart1 status register u1sts=03 006a 16 reserved 0033 16 uart1 control register u1con=00 006b 16 reserved 0034 16 uart1 transmit/receiver buffer 1 u1trb1=xx 006c 16 freq synthesizer control fsc=60 0035 16 uart1 transmit/receiver buffer 2 u1trb2=xx 006d 16 freq synthesizer multiply register 1 fsm1=ff 0036 16 uart1 rts control register u1rtsc=80 006e 16 freq synthesizer multiply register 2 fsm2=ff 0037 16 reserved 006f 16 freq synthesizer divide register fsd=ff
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification processor modes 7/9/98 2-17 2.5 processor modes the operation modes are described below. the memory maps for the first three modes are shown in figure 2-15. single chip mode is normally entered after reset. however, if the mcu has a cnv ss pin, holding this pin high will cause microprocessor mode to be entered after reset. after the reset sequence has completed, the mode can be changed with software by modifying the value of bits 0 and 1 of cpma. however, while cnv ss is high, bit 1 of cpma is 1 and cannot be changed. figure 2-15. operation modes memory maps 2.5.1 single chip in this mode, all ports take on their primary function and all internal memory is accessible. those areas that are not in internal memory are not accessible. also, slow memory wait and edma are disabled in this mode. 0000 0007 0008 000f 0010 006f 0070 00ff 0100 046f 0470 7fff 8000 807f 8080 ffc9 ffca fffb fffc ffff p0-p3 reserved area inaccessible area internal ram (zero page) internal ram rom interrupt vectors reserved area 0000 0007 0008 000f 0010 006f 0070 00ff 0100 046f 0470 7fff 8000 807f 8080 ffc9 ffca fffb fffc ffff external memory reserved area internal ram (zero page) internal ram external memory rom interrupt vectors reserved area 0000 0007 0008 000f 0010 006f 0070 00ff 0100 046f 0470 ffff external memory internal ram (zero page) internal ram external memory sfr sfr sfr single chip mode memory expansion mode microprocessor mode cpma, cpmb,& int registers cpma, cpmb,& int registers cpma, cpmb,& int registers
2-18 7/9/98 processor modes 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.5.2 memory expansion in this mode, ports 0 and 1 output the address bus (ab 0 -ab 15 ), port 2 acts as the data bus input and output, and port 3 bits 7 to 3 output rd, wr, syncout, f out, and dmaout, respectively. all memory areas that are not internal memory or sfr area are accessed externally. because ports 0 to 3 lose their normal function in this mode, the address area for the ports and their direction registers are treated as external memory (see figure 2-15.) in this mode, slow memory wait and edma can be enabled. 2.5.3 microprocessor this mode is primarily the same as memory expansion mode. the difference is that the internal rom / eprom area can not be accessed and is instead treated as external memory. slow memory wait and edma can be enabled in this mode. 2.5.4 eprom this mode is used for programming and testing the internal eprom. in this mode, ports 0 and 1 input the address, port 2 acts as the data bus input and output, and port 3 bits 7, 6, 3 and 2 input oeb, ceb, pgmb, and vrfy, respectively. figure 2-16. function of ports p 0 -p 3 in each processor mode cpma1 cpma0 port p0 0 00 1 1 0 port p1 port p2 port p3 mode port single chip mode microprocessor mode memory expansion mode f internal f internal port p0 7 - p0 0 i/o port port p0 7 - p0 0 address output ab 7 - ab 0 same as microprocessor mode internal port p1 7 - p1 0 i/o port internal port p2 7 - p1 0 i/o port f internal port p1 7 - p1 0 address output ab 15 - ab 8 same as microprocessor mode f internal port p3 7 - p3 0 i/o port f internal port p2 7 - p2 0 data i/o db 7 - db 0 f internal same as microprocessor mode same as microprocessor mode port 3 4 port 3 7 port 3 6 port 3 5 port 3 3 rd output wr output syncout dmaout output f f
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification processor modes 7/9/98 2-19 2.5.5 slow memory wait the wait function is used when interfacing with external memories that are too slow to operate at the normal read/write speed of the mcu. when this is the case, a wait can be used to extend the read/ write cycle. three different wait modes are supported; software wait, rdy wait, and extended rdy wait. the appropriate mode is chosen by the setting of bits 0 to 3 of cpmb. the wait function is disabled for internal memory and is valid only for memory expansion and microprocessor modes. software wait is used to extend the read/write cycle by one, two, or three cycles. the cycle number is determined by the value of bits 0 and 1 of the cpmb. when software wait is selected, the value on the rdy pin is ignored. the timing for software wait is shown in figure 2-17. rdy wait is also used to extend the read/write cycle by one, two, or three cycles. in this case, the read/write cycle is extended if the rdy pin is low a specific amount of time prior to f out going low at the beginning of the read/write cycle. the extension time is fixed by the value of bits 0 and 1 of cpmb and does not depend on the state of the rdy pin when the read/write cycle has begun. if the rdy pin is high at the specified time prior to f out going low at the beginning of the read/write cycle, the cycle is not extended. the timing for rdy wait is shown in figure 2-18.. the extended rdy wait mode is used to extend the read/write cycle by one, two, or three cycles, and then by an additional amount, dependent on the state of the rdy pin. in this mode, initial extension is identical to that of the rdy wait. the state of the rdy pin is checked a specific amount of time prior to the completion of the first cycle of the read/write extension. if the rdy pin is low, the extension is re-initiated from the time that f out goes low at the end of the first cycle of the read/ write extension. the rdy pin continues to be checked until it is brought high. when the rdy pin is brought high, the wait is no longer re-initiated when f out goes low, and the read/write cycle completes in one, two, or three cycles, dependent on the value in bits 0 and 1 of cpmb. the timing for this mode is shown in figure 2-19. the wait function can only be enabled for external memory access in microprocessor or memory expansion modes. however, the wait function can not be enabled for accesses to addresses 0008 16 to 000f 16 (port 0 through port 3 direction registers) in these modes, even though the locations are mapped as external memory.
2-20 7/9/98 processor modes 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-17. software wait timing diagram in out in out in out no wait cpmb = 00 16 one time s/w wait cpmb = 01 16 two time s/w wait cpmb = 02 16 in out three time s/w wait cpmb = 03 16 internal signals x in p1 p2 f out ad out db in/out rd wr rdy x in p1 p2 f out ad out db in/out rd wr rdy
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification processor modes 7/9/98 2-21 figure 2-18. rdy wait timing diagram in out in out in out no wait cpmb = 08 16 one time fixed wait cpmb = 09 16 two time fixed wait cpmb = 0a 16 in out three time fixed wait cpmb = 0b 16 internal signals t su t su t su t su t su t su x in p1 p2 f out ad out db in/out rd wr rdy x in p1 p2 f out ad out db in/out rd wr rdy
2-22 7/9/98 processor modes 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-19. extended rdy wait timing diagram in out in out no wait cpmb = 0c 16 one time extended rdy wait cpmb = 0d 16 two time extended rdy wait cpmb = 0e 16 in out two time extended rdy wait cpmb = oe 16 internal signals t su t su t su t su t su t su three time extended rdy wait cpmb = 0f 16 in t su t su t su t su t su t su t su t su t su out t su t su t su t su t su t su t su t su t su t su t su t su t su t su t su x in p1 p2 f out ad out db in/out rd wr rdy x in p1 p2 f out ad out db in/out rd wr rdy
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification processor modes 7/9/98 2-23 2.5.6 hold function the hold function is used when the mcu is put in a system where more than one device will need control of the external address and data buses. two signals are used to implement this function, hold (p7 1 ) and hlda (p7 3 ). hold is an input to the mcu and is brought low when an external device wants the mcu to relinquish the address and data buses. hlda is an output from the mcu that signals when the mcu has relinquished the buses. when this is the case, the mcu tri-state ports 0 and 1 (address bus) and port 2 (data bus), and holds port p3 7 ( rd) and port p3 6 ( wr) high. ports p3 7 and p3 6 are held high to prevent any external device that is enabled by rd or wr from being falsely activated. the clocks to the cpu are stopped, but the peripheral clocks and port p3 4 ( f out ) continue to oscillate. hold is brought high to allow the mcu to regain the address and data buses. when this occurs, hlda will go high and ports p 1 , p 2 , p3 7 and p3 6 will begin to drive the external buses again. the timing for the hold function is shown in figure 2-20. the hold function is only valid for memory expansion and microprocessor modes. bit 5 of cpmb is used to enable the hold function. hlda will loose its function when the ibf 1 pin functionality is used. figure 2-20. hold mode timing diagram 2.5.7 expanded data memory access the expanded data memory access ( edma) mode feature allows the user to access a greater than 64 kbyte data area for instructions lda (indy) with t = 0 and t = 1, and sta (indy). bit 4 of cpmb is used to enable/disable the edma function. if bit 4 of cpmb equals 1, then during the data read/write cycle of instructions lda (indy) and sta (indy) port 4 0 ( edma) is driven low. the edma signal output can be used by an external decoder to indicate when the read/write is to a different 64 kbyte bank. the actual determination of which bank to access can be done by using a few bits of a port to represent the extended addresses above ab15. for example, if four banks are accessed, then two bits are needed to uniquely identify each bank. two port bits can be used for this, one representing ab16 and the other ab17. the instruction sequences for sta (indy) and lda (indy) are shown in figure 2-21. and figure 2-22. x in p1 p2 p1per p2per f out rd, wr addr out data in/out hold hlda t su (hold- f out ) t h ( f out -hold) t d ( f out -hlda) t d ( f out -hlda)
2-24 7/9/98 processor modes 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-21. sta ($zz),y instruction sequence with edma enabled figure 2-22. lda ($zz),y instruction sequences with edma enabled f sync out rd wr address data adh invalid data next adl+y, adl+y,adh bal+1, 00 bal, 00 pc +1 pc pc + 2 opcode adh+c 91 bal adl edma f sync out rd wr address data adh invalid data next adl+y, adl+y,adh bal+1, 00 bal, 00 pc +1 pc pc + 2 opcode adh+c b1 bal adl edma [lda ($zz),y (t = 0)] instruction sequence ( edma) [lda ($zz),y (t = 1)] instruction sequence ( edma) adh invalid data next adl+y, adl+y,adh bal+1, 00 bal, 00 pc +1 pc pc + 2 opcode adh+c b1 bal adl x, 00 invalid data f sync out rd wr address data edma
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification peripheral interface 7/9/98 2-25 2.6 peripheral interface 2.6.1 chip bus timing the internal bus timing is described below for the cpu (or dmac) writing to and reading from a peripheral (see figure 2-23.) ? the address (ab[15:0]) is output from the cpu on p2. ? the data bus (db[7:0]) is driven by the cpu during a write, or by a peripheral during a read, on p1. ? the r/ w signal is high for a read and low for a write, and changes on p2. ? the eb signal is high when a read or write is not valid, and is low for a valid read or write. it changes on p2. ?a pd n b signal (peripheral decode) is assigned to each peripheral and is low when reading from or writing to the peripheral. each pd n b signal is clocked on p2 timing. the address, r/ w, eb, and pd n b signals are latched at the peripheral block on p1, so they must all be valid before this time. the data bus is latched by the cpu during a read, or by a peripheral during a write, on p2; so the value on the data bus must be valid before this time. figure 2-23. m37640 internal bus timing 2* f p1 p2 ab[15:0], r/w, eb, pdnb [p2] ab[15:0], r/w, eb, pdnb latched @ peripheral [p1 ] ab[2:0], r/w, eb, pdnb peripheral [p1] db[7:0] [p1] db[7:0] latched [p2]
2-26 7/9/98 peripheral interface 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.6.2 peripheral interface and access timing the m37640 offers a wide variety of peripherals. these include ram, eprom, uarts, sios, 8-bit and 16-bit timers, various i/o ports, clock generators, and usb core. the interface between the cpu, the peripheral decode block, and peripheral blocks is shown in figure 2-24. signals db7 to db0, ab2 to ab0, r/w, eb, and at least one peripheral decode (pd n b) are routed to each peripheral. the address signals and peripheral decode signal are used in the peripheral block to create decode signals for each register. because three address bits are available at the peripheral, a maximum of eight decode signals can be created for each peripheral decode signal. if the peripheral contains more than eight registers, additional peripheral decode signals are routed to the peripheral. figure 2-24. internal peripheral interface cpu [p1] [p2] peripheral 1 peripheral 2 peripheral n peripheral decode pd1b pd2b . . . . . . . pdnb reg decode ab pd1 d1 d2 . . dn p1 p1 pd1 r/ w r/w [ab2:0] perdb[7:0] rdbuf db[7:0] p1 p2 p2 ab[2:0], r/w, eb ab[15:0] register n register 2 register 1 p2 r/ w e d1 d1 e r/w wrreg rdreg e
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification peripheral interface 7/9/98 2-27 the bus timing for reading from and writing to a peripheral is shown in figure 2-25. ? when p2 goes high, the address, r/w, and eb are output from the cpu. all address signals are routed to the peripheral decode block where a peripheral decode signal is generated asynchronously. also, data read from a peripheral in the previous half cycle is latched in the cpu, and data written to a peripheral in the previous half cycle is latched in the desired register of the peripheral at this time. ? when p1 goes high, address ab[2:0], r/w, eb, and pdnb are latched at the peripherals. from these signals, the determination of which peripheral and register inside of that peripheral is to be written or read is made. also, if the cpu is writing to a peripheral, it begins to drive the data bus at this time with the data to be written to the peripheral. if the cpu is reading from a peripheral, the peripheral begins to drive the data bus as soon as the decode is ?nished and the data is available from the register. this timing does not apply for the ram, eprom, or usb core. figure 2-25. m37640 peripheral bus timing 2* f p1 p2 cpu: ab, r/w, eb ab, r/w, eb, pdnb latched @peripheral [p1] ab, r/w, eb, pdnb peripheral rdbuf active peripheral decode (pdnb) rdreg perdb db cpu read of db [p2] wrreg[p2] perdb db write to peripheral read from peripheral
2-28 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.7 input and output ports 2.7.1 ports this device has 66 programmable i/o pins arranged as ports p 0 0 to p 8 7 . each port bit can be configured as input or output. to set the i/o port bit direction, write a 1 to the corresponding direction register bit to select output mode, or write a 0 to the direction register bit to select input mode. address description acronym and value at reset address description acronym and value at reset 0008 16 port p0 p0=00 0014 16 port p6 p6=00 0009 16 port p0 direction register p0d=00 0015 16 port p6 direction register p6d=00 000a 16 port p1 p1=00 0016 16 port p5 p5=00 000b 16 port p1 direction register p1d=00 0017 16 port p5 direction register p5d=00 000c 16 port p2 p2=00 0018 16 port p4 p4=00 000d 16 port p2 direction register p2d=00 0019 16 port p4 direction register p4d=00 000e 16 port p3 p3=00 001a 16 port p7 p7=00 000f 16 port p3 direction register p3d=00 001b 16 port p7 direction register p7d=00 0010 16 port control register ptc=00 001c 16 port p8 p8=00 0012 16 port p2 pull-up control register pup2=00 001d 16 port p8 direction register p8d=00 port 2nd function bit 4 0 multiplexed with edma bits 4 1 -4 2 multiplexed with external interrupts int0, int1 bit 4 3 multiplexed with timer x cntr0 pin bit 4 4 multiplexed with timer y cntr1 pin bit 5 0 multiplexed with xc in bit 5 1 multiplexed with timer 1/2 pulse output pin or xc out bit 5 2 multiplexed with obf 0 output to master cpu bit 5 3 multiplexed with ibf 0 output to master cpu bit 5 4 multiplexed with s 0 input from master cpu bit 5 5 multiplexed with a 0 input from master cpu bit 5 6 multiplexed with r (e) input from master cpu bit 5 7 multiplexed with w (r/ w) input from master cpu bits 6 0 -6 7 multiplexed with master cpu bus i/f dq0-dq7 pins bit 7 0 multiplexed with sof bit 7 1 multiplexed with hold bit 7 2 multiplexed with s 1 input from master cpu bit 7 3 multiplexed with ibf 1 or hld a bit 7 4 multiplexed with obf 1 input from master cpu bits 8 0 -8 3 multiplexed with the ?rst alternate function uart2 pins or 2nd alternate function sio pins bits 8 4 -8 7 multiplexed with the uart1 pins
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-29 at reset, all of the direction registers are initialized to 00 16 , setting all of the i/o ports to input mode. if data is written to a pin and then read from that pin while it is in output mode, the data read is the value of the port latch rather than the value of the pin itself. therefore, if an external load changes the value of an output pin, the intended output value will still be read correctly. pins set to input mode are floating (provided that the pull up resistors are not being used) to ensure that the value input to such a pin can be read accurately. in the case when data is written to a pin configured as an input, the data is written only to the port latch; the pin itself remains floating. most of the i/o ports are multiplexed with secondary functions. when a gpi/o is multiplexed with a second function, the control signal from the peripheral overrides the direction register. the multiplexing is briefly described below. the second function signals to and from the i/o ports are described in detail in their respective block's description. 2.7.1.1 i/o ports ports 0, 1, and 3 ports 0 and 1 act as the address bus (ab 0 -ab 15 ) in microprocessor and memory expansion modes. bits 0 and 3-7 of port 3 acts as control signals in microprocessor and memory expansion modes. figure 2-26. port p0, p1, and p3 block diagram port 2 port 2 is an 8-bit general purpose i/o port when in single chip mode. in this mode, the port has key-on wake up circuitry which can be used to restart the chip externally from a wit or stp low power mode. this port also acts as the data bus during microprocessor and memory expansion modes. port 2 input level can be set to reduced vihl level or cmos level by bit 6 of the port control register (ptc). figure 2-27. port p2 block diagram direction register data bus port latch direction register pull-up control data bus port latch key-on wake-up input
2-30 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers port 4 port 4 is a 5-bit general purpose i/o port that can be configured to access special second functions. the port can be set up in any configuration in all three processor modes. port 4 0 this pin is multiplexed with the edma (extended data memory access) function. when the mcu is in memory expansion or microprocessor mode and cpmb4 is set to 1, this pin operates as the edma output as described in section 2.5.7 on page 2-23. figure 2-28. port p4 0 block diagram port 4 1 - 4 2 these pins are multiplexed with external interrupts 0 and 1 (int0 and int1). the external interrupt function is enabled by setting the bits to 1 in the interrupt control register that correspond to int0 and int1. the interrupt polarity register can be configured to define int0 and int1 as active high or low interrupts. see section 2.8.1 on page 2-43 for more information on configuring interrupts. figure 2-29. port p4 1 and p4 2 block diagram port 4 3 - 4 4 these pins are multiplexed with timer x and y functions for pin 4 3 and pin 4 4 respectively. the timer functions of the pins are independently defined by configuring the timer peripheral. pin 4 3 acts as timer x input pin for pulse width measurement mode and event counter mode or as timer x output pin for pulse output mode. pin 4 3 can also be used as an external interrupt (cntr0) when timer x in not in output mode. the polarity is selected in the timer x mode register. the external interrupt function is enabled by setting the bit to 1 in the interrupt control register that direction register data bus port latch cpmb4 edma signal direction register data bus port latch interrupt input
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-31 corresponds to cntr0. see section 2.8.1 on page 2-43 for more information on configuring interrupts. pin 4 4 acts as timer y input pin for pulse period measurement mode, pulse h-l measurement mode, and event counter mode or as timer y output pin for pulse output mode. pin 4 3 can also be used as an external interrupt (cntr1) when timer y in not in output mode. the polarity is selected in the timer y mode register. the external interrupt function is enabled by setting the bit to 1 in the interrupt control register that corresponds to cntr1. see section 2.8.1 on page 2-43 for more information on configuring interrupts. figure 2-30. port p4 3 and p4 4 block diagram port 5 port 5 is an 8-bit general purpose i/o port that can be configured to access special second functions. the port can be set up in any configuration in all three processor modes. port 5 0 this pin is multiplexed with the xc in clock input. when the xc in clock is activated, the pins i/o is disabled. figure 2-31. port p5 0 block diagram direction register data bus port latch cntr0, 1 input timer x, y output timer counter input enable pulse output mode enable direction register data bus port latch cpma4 cpma4 cpma4 xc in input
2-32 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers port 5 1 this pin is multiplexed with the xc out clock output and the timer 1/2 pulse output. when the xc in clock is activated, the pins i/o is disabled. if xc in is not being used as a system clock or xc out oscillation is disabled, the pin can be configured as the timer 1/2 pulse output pin. this feature is configured in the timer123 mode register as described in section 2.13.3 on page 2-87. figure 2-32. port p5 1 block diagram port 5 2 - 5 7 these pins are multiplexed with control pins for the bus interface control block. pin 5 2 acts as obf 0 output to a master cpu when dbbc00 is 1. figure 2-33. port p5 2 block diagram direction register data bus port latch t out enable bit timer 1/2 output direction register data bus port latch dbbc00 obf 0
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-33 pin 5 3 acts as ibf 0 output to a master cpu when dbbc01 is 1. figure 2-34. port p5 3 block diagram pins 5 4 -5 7 act as input control signals from a master cpu when dbbc06 is 1. table 2-2 shows the bus interface control signal that corresponds to each pin. figure 2-35. port p5 4 ~ p5 7 block diagram port 6 port 6 is an 8-bit general purpose i/o port that can be configured to access special second functions. the port acts as the data bus interface for the bus interface control block when dbbc06 is 1. the port can be set up in any configuration in all three processor modes. table 2-2. port p5 4 ~ p5 7 function pin function 5 4 s 0 5 5 a 0 5 6 r(e) 5 7 w(r/ w) direction register data bus port latch dbbc01 ibf 0 data bus port latch see table for function direction register dbbc06 dbbc06
2-34 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-36. port p6 block diagram port 7 port 7 is a 5-bit general purpose i/o port that can be configured to access special second functions. port 7 0 this pin is multiplexed with the usb start of frame pulse ( sof) output. when usbc6 is a 1, this pin outputs the usb sof. figure 2-37. port p7 0 block diagram data bus port latch mbi read status register 1 output buffer 1 a 0 input buffer 0 input buffer 1 status register 1 output buffer 1 a 0 s 0 mbi read s 1 mbi read s 0 mbi write s 1 mbi write mbi write s 0 s 1 direction register direction register data bus port latch usbc6 sof
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-35 port 7 1 this pin is multiplexed with the hold function. when the mcu is in memory expansion or microprocessor mode and cpmb5 is set to 1, this pin operates as the hold input as described in section 2.5.6 on page 2-23. figure 2-38. port p7 1 block diagram port 7 2 this pin is multiplexed with the s 1 input control signal from a master cpu. when dbbc17 is 1, the pin takes on the function of the s 1 input control signal. figure 2-39. port p7 2 block diagram data bus port latch direction register cpmb5 cpmb5 hold data bus port latch direction register dbbc17 dbbc17 s 1
2-36 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers port 7 3 this pin is multiplexed with the ibf 1 output control signal for a master cpu and the hlda function. when dbbc11 and dbbc17 are 1, the pin takes on the function of the ibf 1 output control signal. when the mcu is in memory expansion or microprocessor mode, cpmb5 is set to 1, and the ibf 1 function is not enabled, this pin operates as the hlda output as described in section 2.5.6 on page 2-23. figure 2-40. port p7 3 block diagram port 7 4 this pin is multiplexed with the obf 1 control pin for the bus interface control block. pin 7 4 acts as obf 1 output to a master cpu when dbbc10 and dbbc17 are 1. figure 2-41. port p7 4 block diagram port 8 port 8 is an 8-bit general purpose i/o port that can be configured to access special second functions. the port can be set up in any configuration in all three processor modes. direction register data bus port latch ibf 1 hld a dbbc17 dbbc11 cpmb5 direction register data bus port latch dbbc10 obf 1 dbbc17
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-37 port 8 0 this pin is multiplexed with the sio srdy signal and the uart2 txd signal. when uart2 is in transmit mode, the pin acts as the txd output signal. when the pin is not being used as the uart2 txd output and bit 4 of the sio control register 1 (siocon1) is a 1, the port acts as the sio srdy output signal. if during this function, the sio is configured in slave mode, this pin acts as a slave input from a master. see section 2.15.2 on page 2-102 for more sio information. figure 2-42. port p8 0 block diagram port 8 1 this pin is multiplexed with the sio sclk signal and the uart2 rxd signal. when uart2 is in receive mode, the pin acts as the rxd input signal. when the pin is not being used as the uart2 rxd input and bit 2 of the sio control register 1 (siocon1) is a 1, the port acts as the sio sclk signal. in this mode a 1 in bit 6 of siocon1 configures the pin to output sclk whereas a 0 configures the pin to input sclk. figure 2-43. port p8 1 block diagram direction register data bus port latch sio ready output uart2 txd output uart2 transmit control bit srd y output selection bit sio slave control sio slave mode selection bit sio slave mode selection bit direction register data bus port latch sio clock output sio port selection bit sio clock selection bit sio clock input uart2 receive control bit uart2 receive control bit uart2 receive control bit uart2 rxd input sio clock selection bit
2-38 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers port 8 2 this pin is multiplexed with the sio srxd signal and the uart2 cts signal. when bit 5 of the uart2 control register (u2con) is a 1, the port acts as the cts input signal. when the pin is not being used as the uart2 cts input and bit 2 of the sio control register 2 (siocon2) is a 1, the port acts as the sio srxd input signal. figure 2-44. port p8 2 block diagram port 8 3 this pin is multiplexed with the sio stxd signal and the uart2 rts signal. when bit 6 of the uart2 control register (u2con) is a 1, the port acts as the rts output signal. when the pin is not being used as the uart2 rts output and bit 3 of the sio control register 1 (siocon1) is a 1, the port acts as the sio stxd output signal. figure 2-45. port p8 3 block diagram direction register data bus port latch uart2 cts enable bit sio receive enable bit sio rxd input uart2 cts enable bit uart2 cts input direction register data bus port latch sio txd output uart2 r ts output sio port selection bit transmit complete signal p-channel output disable bit uart2 r ts enable bit
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-39 port 8 4 this pin is multiplexed with the uart1 txd signal. when uart1 is in transmit mode, the pin acts as the txd output signal. figure 2-46. port p8 4 block diagram port 8 5 this pin is multiplexed with the uart1 rxd signal. when uart1 is in receive mode, the pin acts as the rxd input signal. figure 2-47. port p8 5 block diagram port 8 6 this pin is multiplexed with the uart1 cts signal. when bit 5 of the uart1 control register (u1con) is a 1, the port acts as the cts input signal. figure 2-48. port p8 6 block diagram direction register data bus port latch uart1 transmit control bit uart1 txd output direction register data bus port latch uart1 receive control bit uart1 rxd input direction register data bus port latch uart1 cts enable bit uart1 cts input
2-40 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers port 8 7 this pin is multiplexed with the uart1 rts signal. when bit 6 of the uart1 control register (u1con) is a 1, the port acts as the rts output signal. figure 2-49. port p8 7 block diagram 2.7.1.2 power and ground pins there are two v ss and two v dd pins that supply power to the mcu. there is also one analog v dd (av dd ) and one analog v ss (av ss ) pin for the analog circuits. 2.7.1.3 cnv ss pin the level of the signal input to the cnv ss pin at reset determines whether the chip enters single chip or microprocessor mode. with cnv ss connected to v dd , the mcu enters microprocessor mode after a reset. after the reset sequence has been completed, the mode can be changed by modifying the value of bits 0 and 1 of cpma. however, while cnv ss is connected v dd , bit 1 of cpma can not be overwritten. with cnv ss connected to v ss , the mcu enters single chip mode after a reset. 2.7.1.4 x in and x out pins the x in and x out pins are clock input and output pins. this device has a built-in clock generation circuit whose oscillation frequency is set by a quartz oscillator. also, an external clock source can be used by connecting the x in pin to a clock generator and leaving the x out pin floating. the frequency of x in can be 48mhz with an external clock source and 24mhz with a crystal. 2.7.1.5 xc in and xc out pins the p5 0 /xc in and p5 1 /t out /xc out pins are clock input and output pins. this device has a built-in clock generation circuit whose oscillation frequency is set by a ceramic or quartz oscillator. an external clock may also be used by connecting the xc in pin to a clock generator and leaving the xc out pin floating. the frequency of xc in can be 5mhz with an external clock source or 32khz with a crystal. 2.7.1.6 reset pin the mcu is reset by holding reset low for at least 2 m s before returning to high. direction register data bus port latch uart1 r ts enable bit uart1 r ts output
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification input and output ports 7/9/98 2-41 2.7.1.7 rdy pin the p3 0 /rdy pin is used to control the slow memory wait function of the mcu. for a detailed description of this pin, see section 2.5.5 on page 2-19. 2.7.1.8 dmaout pin when the chip is in microprocessor or memory expansion mode, the dmaout (p3 3 /dmaout) pin goes high during a dma transfer. 2.7.1.9 f out pin when the mcu is in microprocessor or memory expansion mode, pin p3 4 outputs the internal system clock f out . when the stp or wit instructions are executed, the output of the f out pin stops at a high level. 2.7.1.10 sync out pin when the mcu is in microprocessor or memory expansion mode, the sync out pin outputs a signal that is high for one-half cycle of f out every time an opcode is fetched. 2.7.1.11 rd and wr pins when the mcu is in microprocessor or memory expansion mode, a read control signal is output from the rd pin and write control signal is output from the wr pin (p3 6 / wr and p3 7 / rd). a low output from the rd pin indicates that the cpu is reading and a low output from the wr pin indicates that the cpu is writing. these signals are active for both internal and external accesses. 2.7.1.12 lpf pin when the frequency synthesizer is active, the lpf pin is the loop filter for the frequency synthesizer. 2.7.1.13 usb d+/d- pins these two pins are used as the data transmission/reception lines for the usb core. 2.7.1.14 ext. cap pin when the usb transceiver voltage converter is used, an external capacitor must be connected to this pin.
2-42 7/9/98 input and output ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.7.2 port control register this device is equipped with a port control register to turn on and off the slew rate control and to control the input levels for port 2 and the mbi pins. (see figure 2-50.). figure 2-50. port control register 2.7.3 port 2 pull-up control register this device is equipped with internal pull-ups on port 2 that can be enabled by software. each bit of the pull-up control register controls a corresponding pin of port 2. the pull-up control register pulls up the port when the port is in input mode. the value of the pull-up control register has no effect when the port is in output mode. figure 2-51. pull-up control register msb 7 lsb 0 ptc4 ptc3 ptc2 ptc1 ptc0 ptc0 slew rate control bit ports 0-3 (bit 0) 0: disabled 1: enabled ptc1 slew rate control bit port 4 (bit 1) 0: disabled 1: enabled ptc2 slew rate control bit port 5 (bit 2) 0: disabled 1: enabled ptc3 slew rate control bit port 6 (bit 3) 0: disabled 1: enabled ptc4 slew rate control bit port 7 (bit 4) 0: disabled 1: enabled ptc5 slew rate control bit port 8 (bit 5) 0: disabled 1: enabled ptc6 port 2 input level select bit (bit 6) 0: reduced vihl level input 1: cmos level input ptc7 master bus input level select bit (bit 7) 0: cmos level input 1: ttl level input access: r/w reset: 00 16 ptc7 ptc6 ptc5 address: 0010 16 pup2 0 pull-up control for port 2 (bit 0) 0: disabled 1: enabled pup2 1 pull-up control for port 2 (bit 1) 0: disabled 1: enabled pup2 2 pull-up control for port 2 (bit 2) 0: disabled 1: enabled pup2 3 pull-up control for port 2 (bit 3) 0: disabled 1: enabled pup2 4 pull-up control for port 2 (bit 4) 0: disabled 1: enabled pup2 5 pull-up control for port 2 (bit 5) 0: disabled 1: enabled pup2 6 pull-up control for port 2 (bit 6) 0: disabled 1: enabled pup2 7 pull-up control for port 2 (bit 7) 0: disabled 1: enabled msb 7 lsb 0 pup2 4 pup2 3 pup2 2 pup2 1 pup2 0 access: r/w reset: 00 16 pup2 7 pup2 6 pup2 5 address: 0012 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification interrupt control unit 7/9/98 2-43 2.8 interrupt control unit the interrupt control unit (icu), a specialized peripheral, is described in detail in this section. this series supports a maximum of 23 maskable interrupts, one software interrupt, and one reset vector that is treated as a non-maskable interrupt. see table 2-3 for the interrupt sources, jump destination addresses, interrupt priorities, and section references for the interrupt request sources. 2.8.1 interrupt control each maskable interrupt has associated with it an interrupt request bit and an interrupt enable bit. these bits, along with the i flag, determine whether interrupt events can cause an interrupt service request to be generated. an interrupt request bit is set to at 1 when its corresponding interrupt event is activated. the bit is cleared to a 0 when the interrupt is serviced or when a 0 is written to the bit. the bit can not be set high by writing 1 to it. each interrupt enable bit determines whether the interrupt request bit it is paired with is seen when the interrupts are polled. when the interrupt enable bit is a 0, the interrupt request bit is not seen; and when the enable bit is a 1, the interrupt request is seen. the interrupt request register configurations for the 23 maskable interrupts are shown in figure 2-52., figure 2-53., and figure 2-54. the interrupt control register configurations for the 23 maskable interrupts are shown in figure 2-55., figure 2-56., and figure 2-57. figure 2-52. ireqa con?guration address description acronym and value at reset address description acronym and value at reset 0002 16 interrupt request register a ireqa=00 0006 16 interrupt control register b iconb=00 0003 16 interrupt request register b ireqb=00 0007 16 interrupt control register c iconc=00 0004 16 interrupt request register c ireqc=00 0011 16 interrupt polarity selection register ipol=00 0005 16 interrupt control register a icona=00 ira0 usb function interrupt request (bit 0) ira1 usb sof interrupt request (bit 1) ira2 external interrupt 0 request (bit 2) ira3 external interrupt 1 request (bit 3) ira4 dmac channel 0 interrupt request (bit 4) ira5 dmac channel 1 interrupt request (bit 5) ira6 uart1 receive buffer full interrupt request (bit 6) ira7 uart1 transmit interrupt request (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 ira7 ira6 ira5 ira4 ira3 ira2 ira1 ira0 access: r/w reset: 00 16 address: 0002 16
2-44 7/9/98 interrupt control unit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-53. ireqb con?guration figure 2-54. ireqc con?guration figure 2-55. icona con?guration figure 2-56. iconb con?guration irb0 uart1 error sum interrupt request (bit 0) irb1 uart2 receive buffer full interrupt request (bit 1) irb2 uart2 transmit interrupt request (bit 2) irb3 uart2 error sum interrupt request (bit 3) irb4 timer x interrupt request (bit 4) irb5 timer y interrupt request (bit 5) irb6 timer 1 interrupt request (bit 6) irb7 timer 2 interrupt request (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 irb7 irb6 irb5 irb4 irb3 irb2 irb1 irb0 access: r/w reset: 00 16 address: 0003 16 irc0 timer 3 interrupt request (bit 0) irc1 external cntr0 interrupt request (bit 1) irc2 external cntr1 interrupt request (bit 2) irc3 sio interrupt request (bit 3) irc4 input buffer full interrupt request (bit 4) irc5 output buffer empty interrupt request (bit 5) irc6 key-on wake-up interrupt request (bit 6) 0: no interrupt request issued 1: interrupt request issued bit 7 reserved (read/write 0) msb 7 lsb 0 reserved irc6 irc5 irc4 irc3 irc2 irc1 irc0 access: r/w reset: 00 16 address: 0004 16 ica0 usb function interrupt enable (bit 0) ica1 usb sof interrupt enable (bit 1) ica2 external interrupt 0 enable (bit 2) ica3 external interrupt 1 enable (bit 3) ica4 dmac channel 0 interrupt enable (bit 4) ica5 dmac channel 1 interrupt enable (bit 5) ica6 uart1 receive buffer full interrupt enable (bit 6) ica7 uart1 transmit interrupt enable (bit 7) 0: interrupt disable 1: interrupt enable msb 7 lsb 0 ica7 ica6 ica5 ica4 ica3 ica2 ica1 ica0 access: r/w reset: 00 16 address: 0005 16 icc0 uart1 error sum interrupt enable (bit 0) icc1 uart2 receive buffer full interrupt enable (bit 1) icc2 uart2 transmit interrupt enable (bit 2) icc3 uart2 error sum interrupt enable (bit 3) icc4 timer x interrupt enable (bit 4) icc5 timer y interrupt enable (bit 5) icc6 timer 1 interrupt enable (bit 6) icc7 timer 2 interrupt enable (bit 7) 0: interrupt disable 1: interrupt enable msb 7 lsb 0 icb7 icb6 icb5 icb4 icb3 icb2 icb1 icb0 access: r/w reset: 00 16 address: 0006 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification interrupt control unit 7/9/98 2-45 figure 2-57. iconc con?guration the interrupt polarity register allows the user to select the external interrupt edge which triggers the interrupt request. the configuration of the polarity register for the external interrupts is shown in figure 2-58. figure 2-58. ipol con?guration icc0 timer 3 interrupt enable (bit 0) icc1 external cntr0 interrupt enable (bit 1) icc2 external cntr1 interrupt enable (bit 2) icc3 sio interrupt enable (bit 3) icc4 input buffer full interrupt enable (bit 4) icc5 output buffer empty interrupt enable (bit 5) icc6 key-on wake-up interrupt enable (bit 6) 0: interrupt disabled 1: interrupt enabled bit 7 reserved (read/write 0) msb 7 lsb 0 reserved icc6 icc5 icc4 icc3 icc2 icc1 icc0 access: r/w reset: 00 16 address: 0007 16 int0 pol int0 interrupt edge selection bit 0: falling edge selected. 1: rising edge selected. int1 pol int1 interrupt edge selection bit 0: falling edge selected. 1: rising edge selected. bits 2-7 reserved (read/write 0) msb 7 lsb 0 int1 pol int0 pol access: r/w reset: 00 16 address: 0011 16 reserved reserved reserved reserved reserved reserved
2-46 7/9/98 interrupt control unit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers table 2-3 interrupt vector table priority interrupt jump destination storage address (vector address) remarks high-order byte low-order byte reference 1 rsrv1 ffff fffe reserved for factory use corresponding register assignment 2 rsrv2 fffd fffc reserved for factory use 3 reset fffb fffa user reset (non-maskable) 4 usb fff9 fff8 usb function interrupt 0 lsb ireqa and icona section 2.9.2.1 5 sof fff7 fff6 usb sof interrupt 1 section 2.9.2.2 6 int0 fff5 fff4 external interrupt 0 2 section 2.8.1 7 int1 fff3 fff2 external interrupt 1 3 section 2.8.1 8 dma1 fff1 fff0 dmac channel 0 interrupt 4 section 2.11 9 dma2 ffef ffee dmac channel 1 interrupt 5 section 2.11 10 u1rbf ffed ffec uart1 receiver buffer full 6 section 2.14.7 11 u1tx ffeb ffea uart1 transmit interrupt 7 msb section 2.14.7 12 u1es ffe9 ffe8 uart1 error sum interrupt 0 lsb ireqb and iconb section 2.14.7 13 u2rbf ffe7 ffe6 uart2 receiver buffer full 1 section 2.14.7 14 u2tx ffe5 ffe4 uart2 transmit interrupt 2 section 2.14.7 15 u2es ffe3 ffe2 uart2 error sum interrupt 3 section 2.14.7 16 tx ffe1 ffe0 timer x interrupt 4 section 2.13 17 ty ffdf ffde timer y interrupt 5 section 2.13 18 t1 ffdd ffdc timer 1 interrupt 6 section 2.13 19 t2 ffdb ffda timer 2 interrupt 7 msb section 2.13 20 t3 ffd9 ffd8 timer 3 interrupt 0 lsb ireqc and iconc section 2.13 21 cntr0 ffd7 ffd6 external cntr0 interrupt 1 section 2.13.1.6 22 cntr1 ffd5 ffd4 external cntr1 interrupt 2 section 2.13.2 23 sio ffd3 ffd2 sio interrupt 3 section 2.15 24 ibf ffd1 ffd0 input buffer full interrupt 4 section 2.10 25 obe ffcf ffce output buffer empty interrupt 5 section 2.10 26 key ffcd ffcc key-on wake up 6 msb section 2.18 27 brk ffcb ffca brk instruction (non-maskable)
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification interrupt control unit 7/9/98 2-47 2.8.2 interrupt sequence and timing the interrupts are polled prior to the beginning of each instruction. an interrupt service request is generated when an interrupt event has its interrupt request bit set to a 1, its interrupt enable bit is set to a 1, and the interrupt inhibit flag i is set low. the i flag is used to disable all maskable interrupts. when this bit is set to a 1, only a brk instruction or a user reset can cause an interrupt service request to be generated. figure 2-59 is a simplified version of the logic that controls whether an interrupt service request is generated. figure 2-59. interrupt service request control logic the time elapsed from the occurrence of an interrupt event until execution of its service routine varies from 7 cycles to 23 cycles, depending on what instruction is executing when the interrupt event occurs (see figure 2-60.) figure 2-60. execution time prior to interrupt service routine when an interrupt service request occurs, the current instruction stream is temporarily halted and the appropriate interrupt service routine is executed. after the interrupt service routine ends, the current instruction stream is resumed with the next instruction. the interrupt service request causes the mcu to automatically push the high-order byte of the program counter, the low-order byte of the program counter, and the contents of the processor status register onto the stack. a push consists of storing data at the stack address and decrementing the stack pointer by one as illustrated in figure 2-2. the i flag is set to a 1 to prevent other interrupts from being serviced during the interrupt service routine, and the request bit corresponding to the interrupting event is automatically cleared to 0. the program counter is set to the address specified in the vector table for the interrupt being serviced. this address contains the address for the first instruction of the interrupt service routine. the timing for the pushing of data onto the stack, and fetching the starting address of the interrupt routine is illustrated in figure 2-61. interrupt request bit interrupt enable bit interrupt inhibit flag i brk instruction reset interrupt request interrupt request 23 to 7 cycles (1.92 m s to 0.583 m s, when f( f ) = 12 mhz) maximum 16 cycles * 2 cycles, 5 cycles, interrupt processing minimum 0 cycles dummy cycles for pipeline postprocessing stack push and vector fetch routine current instruction * for div instruction
2-48 7/9/98 interrupt control unit 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-61. interrupt cycle timing see figure 2-62. for the stack and program counter modifications that occur when an interrupt request is serviced. figure 2-62. stack pointer and program counter modi?cations during interrupt service sequence returning from an interrupt is accomplished by executing an rti instruction. this causes the mcu to pop the contents of the process status register and the low-order and high-order bytes of the program counter from the stack. the i flag is cleared to 0 when the process status value is restored from the stack. f out p1 p2 sync out rd wr address data invalid invalid pch pcl ps adl adh next adl,adh (int vector)l s-2,cpma2 s-1,cpma2 s,cpma2 pc pc (int vector)h opcode program counter program counter (l) program counter (h) stack pointer (s) program counter loaded values of the vector stack pointer (s) - 3 stack (in zero/one page) pc l pc h pc l pc h s address corresponding to the accepted interrupt. interrupt enable interrupt disable interrupt accept (s) - 3 (s) (s) stack (in zero/one page) processor status register program counter (l) program counter (h) s
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-49 2.9 universal serial bus the universal serial bus (usb) has the following features: ? complete usb speci?cation (version 1.0) compatibility ? error handling capabilities ? fifos: ? endpoint 0: in 16-byte out 16-byte ? endpoint 1: in 512-byte out 800-byte ? endpoint 2: in 32-byte out 32-byte ? endpoint 3: in 16-byte out 16-byte ? endpoint 4: in 16-byte out 16-byte ? five independent in and ?ve independent out endpoints ? complete device con?guration ? supports all device commands ? supports full-speed functions ? support of all usb transfer types: ? isochronous ? bulk ? control ? interrupt ? suspend/resume operation ? on-chip usb transceiver with voltage converter ? start-of-frame interrupt and output pin address description acronym and value at reset address description acronym and value at reset 0013 16 usb control register usbc=00 005a 16 usb endpoint x out csr out_csr=00 0050 16 usb address register usba=00 005b 16 usb endpoint x in maxp in_maxp 0051 16 usb power management register usbpm=00 005c 16 usb endpoint x out maxp out_maxp 0052 16 usb interrupt status register 1 usbis1=00 005d 16 usb endpoint x out wrt cnt low wrt_cntl=00 0053 16 usb interrupt status register 2 usbis2=00 005e 16 usb endpoint x out wrt cnt high wrt_cnth=00 0054 16 usb interrupt enable register 1 usbie1=ff 005f 16 reserved 0055 16 usb interrupt enable register 2 usbie2=33 0060 16 usb endpoint 0 fifo usbfifo0=n/a 0056 16 usb frame number low register usbsofl=00 0061 16 usb endpoint 1 fifo usbfifo1=n/a 0057 16 usb frame number high register usbsofh=00 0062 16 usb endpoint 2 fifo usbfifo2=n/a 0058 16 usb endpoint index usbindex=00 0063 16 usb endpoint 3 fifo usbfifo3=n/a 0059 16 usb endpoint x in csr in_csr=00 0064 16 usb endpoint 4 fifo usbfifo4=n/a
2-50 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.9.1 usb function control unit (usb fcu) the implementation of the usb by this device is accomplished chiefly through the devices usb function control unit. the function control units overall purpose is to handle the usb packet protocol layer. the function control unit notifies the mcu that a valid token has been received. when this occurs, the data portion of the token is routed to the appropriate fifo. the mcu transfers the data to, or from, the host by interacting with that endpoints fifo and csr register. (see figure 2-63.) the usb function control unit is composed of five sections: ? serial interface engine (sie) ? generic function interface (gfi) ? serial engine interface unit (siu) ? microcontroller interface (mci) ? usb transceiver 2.9.1.1 serial interface engine the sie interfaces to the usb serial data and handles deserialization/serialization of data, nrzi encoding decoding, clock extraction, crc generation and checking, bit stuffing, and other specifications pertaining to the usb protocol such as handling inter-packet time-outs and pid decoding. 2.9.1.2 generic function interface the gfi handles the all usb standard requests from the host through the control endpoint (endpoint zero), handles bulk, isochronous and interrupt transfers through endpoints 1-4. the gfi handles read pointer reversal for re-transmit the current data set; write pointer reversal for re-receive the last data set; data toggle synchronization. 2.9.1.3 serial engine interface unit the siu block decodes the address and endpoint fields from the usb host. 2.9.1.4 microcontroller interface unit the mci block handles the microcontroller interface and performs address decoding and synchronization of control signals. 2.9.1.5 usb transceiver the usb transceiver, designed to interface with the physical layer of the usb, is compliant with the usb specification (version 1.0) for high speed devices. it consists of two 6-ohm drivers, a receiver, and schmitt triggers for single-ended receive signals. the transceiver also includes a voltage converter. the voltage converter can supply 3.0 - 3.6v to the transmitter when the rest of the chip (cpu, usb fcu, etc...) operates at 4.15 - 5.25v. to enable the voltage converter, set bit 4 of the usb control register (usbc) to a 1. to disable the voltage converter, set bit 4 of the usbc to a 0. refer to section 4.5 usb transceiver for more detailed information.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-51 figure 2-63. usb function control unit block diagram 2.9.2 usb interrupts there are two types of usb interrupts in this device: the first type is the usb function (including overrun/underrun, reset, suspend and resume) interrupt, used to control the flow of data and usb power control; the second type is start-of-frame (sof) interrupt, used to monitor the transfer of isochronous (iso) data. 2.9.2.1 usb function interrupt endpoint 1-4, each has two interrupt status bits associated with it to control the data transfer or to report a stall/under_run/over_run condition. the epx_out_int bit is set when the usb fcu successfully receives a packet of data, or sets the force_stall bit, or the over_run bit of the endpoint x out csr. the epx_in_int bit is set when the usb fcu successfully sends a packet of data, or sets the under_run bit of the endpoint x in csr. endpoint 0 - the control endpoint - has one interrupt status bit associated with it to control the data transfer or report a stall condition. the ep0_int is set when the usb fcu successfully receives/sends a packet of data, or sets the setup_end bit, the force_stall bit, or clears the data_end bit in the endpoint 0 in csr. each endpoint interrupt is enabled by setting the corresponding bit in the usb interrupt enable register 1 and 2. the usb interrupt status register 1 and 2 are used to indicate pending interrupts for a given endpoint. the usb fcu sets the interrupt status bits. the cpu writes a 1 to clear the corresponding status bit. by writing back the same value it read, the cpu will clear all the existing interrupts. the cpu must read then write both status registers, writing status register 1 first and status register 2 second to guarantee proper operation. the suspend interrupt status bit is set if a usb suspend signaling is received. if the device is in suspend mode, the resume interrupt status bit is set when a usb resume signaling is received. there is a single interrupt enable bit for both of suspend and resume interrupts (bit 7 of the interrupt enable register 2). the usb reset interrupt status bit is set if a usb reset signaling is received. when this bit is set, all usb internal registers will be reset to their default values except this bit itself. this bit is cleared by the cpu writing a 0 to it. when the cpu detects a usb reset interrupt, it needs to re-initialize the usb block in order to accept packets from the host. cpu mci siu gfi fifos sie transceiver d + d -
2-52 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers the over/underrun status bit is set (applicable to endpoints used for isochronous data transfer), when an overrun condition occurs in an endpoint (cpu is too slow to unload the data from the fifo), or when an underrun condition occurs in an endpoint (cpu is too slow to load the data to the fifo). the usb function interrupt (sum of all individual function interrupts) is enabled by setting the corresponding bit in the interrupt control register of the interrupt control unit. 2.9.2.2 usb sof interrupt the usb sof (start-of-frame) interrupt is used to control the transfer of isochronous data. the usb fcu generates a start-of-frame interrupt when a start-of-frame packet is received. the usb sof interrupt is enabled by setting the corresponding bit in the interrupt control register of the interrupt control unit. 2.9.3 usb endpoint fifos the usb fcu has an in (transmit) fifo and an out (receive) fifo for each endpoint. both fifos support up to two separate data sets of variable size (except endpoint 0), and provide the ability of back-to-back transmission and reception. throughout this specification, the terms in fifo and out fifo refer these fifos associated with the current endpoint as specified by the endpoint index register. in the event of a bad transmission/reception, the usb fcu handles all the read/write pointer reversal and data set management tasks when it is applicable. 2.9.3.1 in (transmit) fifos the cpu/dma writes data to the endpoints in fifo location specified by the fifo write pointer, which automatically increments by "1" after a write. the cpu/dma should only write data to the in fifo if the in_pkt_rdy bit of the in csr is a 0. endpoint 0 in fifo operation : the cpu writes a 1 to the in_pkt_rdy bit after it finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit after the packet is successfully transmitted to the host (ack is received from the host) or the setup_end bit of the in csr is set to a 1. endpoint 1-4 in fifo operation when auto_set (bit 7 of in csr) = 0 : maxp > half of the in fifo size: the cpu writes a 1 to in_pkt_rdy bit after the cpu/dmac finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit after the packet is successfully transmitted to the host (ack is received from the host). maxp <= half of the in fifo size: the cpu writes a 1 to the in_pkt_rdy bit after the cpu/ dmac finishes writing a packet of data to the in fifo. the usb fcu clears the in_pkt_rdy bit as soon as the in fifo is ready to accept another data packet (the fifo can hold up to two data packets at the same time in this configuration, for back-to-back transmission). since the set and the clear operations could be as fast as 83ns (one 12mhz clock period) apart from each other, the set may be transparent to the user. endpoint 1-4 in fifo operation when auto_set (bit 7 of in csr) = 1 : maxp > half of the in fifo size: when the number of bytes of data equal to the maxp (maximum packet size) is written to the in fifo by the cpu/dmac, the usb fcu sets the in_pkt_rdy bit to a 1 automatically. the usb fcu clears the in_pkt_rdy bit after the packet is successfully transmitted to the host (ack is received from the host).
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-53 maxp <= half of the in fifo size: when the number of bytes of data equal to the maxp (maximum packet size) is written to the in fifo by the cpu/dmac, the usb fcu sets the in_pkt_rdy bit to a 1 automatically. the usb fcu clears the in_pkt_rdy bit as soon as the in fifo is ready to accept another data packet (the fifo can hold up to two data packets at the same time in this configuration, for back-to-back transmission). since the set and the clear operations could be as fast as 83ns (one 12mhz clock period) apart from each other, the set may be transparent to the user. a software or a hardware flush acts as if a packet is being successfully transmitted out to the host. if there is one packet in the in fifo, a flush will cause the in fifo to be empty, if there are two packets in the in fifo, a flush will cause the older packet to be flushed out from the in fifo. flush will update the in fifo status (in_pkt_rdy and tx_not_empty bits). the status of the endpoint 1-4 in fifo for both of the above cases, could be obtained from the in csr as follows: interrupt endpoints: any endpoint can be used for interrupt transfers. for normal interrupt transfers, the interrupt transactions behave the same as bulk transactions, i.e., no special setting is required. the in endpoints may also be used to communicate rate feedback information for certain types of isochronous functions. this is done by setting the intpt bit in the in csr register of the corresponding endpoint. when the intpt bit is set, the data toggle bits will be changed after each packet is sent to the host without regard to the presence or type of handshake packet. the following outlines the operation sequence for an in endpoint used to communicate rate feedback information: 1. set maxp > 1/2 of the endpoints fifo size; 2. set intpt bit of the in csr; 3. flush the old data in the fifo; 4. load interrupt status information and set in_pkt_rdy bit in the in csr; 5. repeat steps 3 & 4 for all subsequent interrupt status updates. 2.9.3.2 out (receive) fifos the usb fcu writes data to the endpoints out fifo location specified by the fifo write pointer, which automatically increments by one after a write. when the usb fcu has successfully received a data packet, it sets the out_pkt_rdy bit to a 1 in the out csr. the cpu/dmac should only read data from the out fifo if the out_pkt_rdy bit of the out csr is a 1, with the exception of endpoint 1 (see detail description below). endpoint 0 out fifo operation : the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the cpu writes a 0 to the out_pkt_rdy bit after the packet of data is unloaded from the out fifo by the cpu. endpoint 1-4 out fifo operation when auto_clr (bit 7 of out csr) = 0 : in_pkt_rdy tx_not_empty tx fifo status 0 0 no data packet in tx fifo 0 1 one data packet in tx fifo if maxp <= half of the fifo size. 1 0 invalid 11 two data packets in tx fifo if maxp <= half of the fifo size or one data packet in tx fifo if maxp > half of the fifo size
2-54 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers maxp > half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the cpu writes a 0 to the out_pkt_rdy bit after the packet of data is unloaded from the out fifo by the cpu/dmac. maxp <= half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the cpu writes a 0 to the out_pkt_rdy bit after the packet of data is unloaded from the out fifo by the cpu/dmac. in this configuration, the fifo can hold upto two data packets at the same time, for back-to-back reception. therefore, the out_pkt_rdy bit may remain set after the cpu writes a 0 to it if there is another packet in the out fifo. endpoint 1-4 out fifo operation when auto_clr (bit 7 of out csr) = 1 : maxp > half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the usb fcu clears the out_pkt_rdy bit to a 0 automatically when the number of bytes of data equal to the maxp (maximum packet size) is unloaded from the out fifo by the cpu/dmac. maxp <= half of the out fifo size: the usb fcu sets the out_pkt_rdy bit to a 1 after it has successfully received a packet of data from the host. the usb fcu clears the out_pkt_rdy bit to a 0 automatically when the number of bytes of data equal to the maxp (maximum packet size) is unloaded from the out fifo by the cpu/dmac. in this configuration, the fifo can hold up to two data packets at the same time, for back-to-back reception. therefore, the out_pkt_rdy bit may remain set after one packet (size equal to maxp) of data is unloaded if there is another packet in the out fifo. a software flush acts as if a packet is being unloaded from the out fifo. if there is one packet in the out fifo, a flush will cause the out fifo to be empty, if there are two packets in the out fifo, a flush will cause the older packet to be flushed out from the out fifo. special case for out endpoint 1 : in addition to the out fifo operations described above, the dmac can also start unloading the out fifo as soon as there is data in it (byte-by-byte transfer). this feature should only be used with iso transfers. see section 2.11 "direct memory access controller" on page 2-69 for details. 2.9.4 usb special function registers the mcu controls usb operation through the use of special function registers (sfr). this section describes in detail each usb related sfr. certain usb sfrs are endpoint-indexed: the control & status registers (in csr and out csr), the maximum packet size registers (in maxp and out maxp), and the write count registers (out wrt cnt). to access each endpoint-indexed sfr, the target endpoint number should be written to the endpoint index register first. the lower 3 bits (epindx2:0) of the endpoint index register are used for endpoint selection. note: each endpoints fifo register is not endpoint-indexed. some usb special function registers have a mix of read/write, read only, and write only register bits. additionally, the bits may be configured to allow the user to write only a 0 or a 1 to individual bits. when accessing these registers, writing a 0 to a register that can only be set to a 1 by the cpu will have no affect on that register bit. each figure and description of the special function registers will detail this operation. the usb control register, shown in figure 2-64 , is used to control the usb fcu. this register is not reset by a usb reset signaling. after the usb is enabled (usbc7 set to 1), a minimum delay of 250 ns (three 12mhz clock periods) is needed before performing any other usb register read/write operations.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-55 figure 2-64. usb control register the usb function address register , shown in figure 2-65, maintains the 7-bit usb address assigned by the host. the usb fcu uses this register value to decode usb token packet addresses. at reset, when the device is not yet configured, the value is 00 16 . figure 2-65. usb function address register the usb power management register , shown in figure 2-66, is used for power management in the usb fcu. usb suspend detection flag when the usb fcu receives a usb suspend signaling, it sets the suspend bit and generates an inter- rupt. the cpu writes a 0 to clear this bit when the device is resumed by the host (resume interrupt is gen- erated and resume detection flag is set) or remote wake-up by itself (the cpu writes a 1 to remote wake-up bit). usb resume detection flag when the usb fcu is in suspend mode and receives a usb resume signaling, it sets the resume bit, and generates an interrupt. the cpu writes a 0 to clear this bit. usb remote wake-up bit the cpu writes a 1 to the wakeup bit for remote wake-up. while this bit is set, and the usb fcu is in suspend mode, it will generate a resume signaling to the host. the cpu must keep this bit set for a min- imum of 10ms and a maximum of 15ms before writing a 0 to this bit. bit 0 reserved (read/write 0) usbc1 usb default state selection bit (bit 1) 0: in default state after powerup/reset 1: in default state after received the usb reset signaling bit 2 reserved (read/write 0) usbc3 transceiver voltage converter high/low current mode selection bit (bit 3) 0: high current mode 1: low current mode usbc4 usb transceiver voltage converter enable bit (bit 4) 0: usb transceiver voltage converter disabled 1: usb transceiver voltage converter enabled usbc5 usb clock enable bit (bit 5) 0: 48 mhz clock to the usb block is disabled. 1: 48 mhz clock to the usb block is enabled. usbc6 usb sof port select bit (bit 6) 0: usb sof output is disabled. p7 0 is used as gpio pin. 1: usb sof output is enabled usbc7 usb enable bit (bit 7) 0: usb block is disabled, all usb internal registers are held at their default values. 1: usb block is enabled msb 7 lsb 0 usbc7 usbc6 usbc5 usbc4 usbc3 usbc1 reserved access: r/w reset: 00 16 address: 0013 16 reserved funad6:0 7-bit programmable function address (bits 6-0) bit 7 reserved (read/write 0) msb 7 lsb 0 reserved funad6 funad5 funad4 funad3 funad1 funad0 access: r/w reset: 00 16 funad2 address: 0050 16
2-56 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-66. usb power management register the usb fcu is able to generate a usb function interrupt as discussed in section 2.9.2.1. the usb interrupt status registers, shown in figure 2-67 and figure 2-68, are used to indicate the condition that caused a usb function interrupt to the cpu. a 1 indicates the corresponding condition caused a usb function interrupt. the usb interrupt status registers can be cleared by writing back to the register the same value that was read. to ensure proper operation, the cpu should read both usb interrupt status registers, then write back the same values it read to these two registers for clearing the status bits. the cpu must write the usb interrupt status register 1 first, then the usb interrupt status register 2. the registers cannot be cleared by writing a 0 to the bits that are a 1. the usb interrupt enable registers, shown in figure 2-69 and figure 2-70, are used to enable the corresponding interrupt status conditions, which can generate a usb function interrupt. if the bit to a corresponding interrupt condition is 0, that condition will not generate a usb function interrupt. if the bit is a 1, that condition can generate a usb function interrupt. upon reset, all usb interrupt status conditions are enabled except bit 7 of usb interrupt enable register 2 - i.e., suspend and resume interrupt is disabled. figure 2-67. usb interrupt status register 1 intst0 is set to a 1 by the usb fcu if (in endpoint 0 in csr): ? successfully receives a packet of data ? successfully sends a packet of data ? in0csr3 (data_end) bit is cleared ? in0csr4 (force_stall) bit is set ? in0csr5 (setup_end) bit is set intst2 , intst4 , intst6 or intst8 is set to a 1 by the usb fcu if (in endpoint x in csr): ? successfully sends a packet of data ? inxcsr1 (under_run) bit is set suspend usb suspend detection flag (bit 0) (write 0 only or read) 0: no usb suspend signal detected 1: usb suspend signal detected resume usb resume detection flag (bit 1) (write 0 only or read) 0: no usb resume signal detected 1: usb resume signal detected wakeup usb remote wake-up bit (bit 2) 0: end remote resume signaling 1: remote resume signaling (if suspend = 1) bit7:3 reserved (read/write 0) msb 7 lsb 0 reserved reserved reserved reserved reserved resume suspend access: r/w reset: 00 16 wakeup address: 0051 16 intst0 usb endpoint 0 interrupt status flag (bit 0) bit 1 reserved (read/write 0) intst2 usb endpoint 1 in interrupt status flag (bit 2) intst3 usb endpoint 1 out interrupt status flag (bit 3) intst4 usb endpoint 2 in interrupt status flag (bit 4) intst5 usb endpoint 2 out interrupt status flag (bit 5) intst6 usb endpoint 3 in interrupt status flag (bit 6) intst7 usb endpoint 3 out interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 intst7 intst6 intst5 intst4 intst3 reserved intst0 access: r/w reset: 00 16 intst2 address: 0052 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-57 intst3, intst5 , intst7 or intst9 is set to a 1 by the usb fcu if (in endpoint xout csr): ? successfully receives a packet of data ? outxcsr1 (over_run) bit is set ? outxcsr4 (force_stall) bit is set figure 2-68. usb interrupt status register 2 intst12 is set to a 1 by the usb fcu if an overrun or underrun condition occurs in any of the endpoints. intst13 is set to a 1 by the usb fcu if a usb reset signaling from the host is received. all usb internal registers will be reset to their default values except this bit. intst14 is set to a 1 by the usb fcu if a usb resume signaling is received from the host. intst15 is set to a 1 by the usb fcu if a usb suspend signaling is received from the host. figure 2-69. usb interrupt enable register 1 figure 2-70. usb interrupt enable register 2 intst8 usb endpoint 4 in interrupt status flag (bit 0) intst9 usb endpoint 4 out interrupt status flag (bit 1) bit 3:2 reserved (read/write 0) intst12 usb overrun/underrun interrupt status flag (bit 4) intst13 usb reset interrupt status flag (bit 5) intst14 usb resume signaling interrupt status flag (bit 6) intst15 usb suspend signaling interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 intst15 intst14 intst13 intst12 reserved intst9 intst8 access: r/w reset: 00 16 address: 0053 16 reserved inten0 usb endpoint 0 in interrupt enable bit (bit 0) bit 1 reserved (read/write 0) inten2 usb endpoint 1 in interrupt enable bit (bit 2) inten3 usb endpoint 1 out interrupt enable bit (bit 3) inten4 usb endpoint 2 in interrupt enable bit (bit 4) inten5 usb endpoint 2 out interrupt enable bit (bit 5) inten6 usb endpoint 3 in interrupt enable bit (bit 6) inten7 usb endpoint 3 out interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled msb 7 lsb 0 inten7 inten6 inten5 inten4 inten3 reserved inten0 access: r/w reset: ff 16 inten2 address: 0054 16 inten8 usb endpoint 4 in interrupt enable bit (bit 0) inten9 usb endpoint 4 out interrupt enable bit (bit 1) bit 3:2 reserved (read/write 0) inten12 usb overrun/underrun interrupt enable bit (bit 4) inten13 usb reset interrupt enable bit (bit 5) bit 6 reserved (read/write 0) inten15 usb suspend/resume signaling interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled msb 7 lsb 0 inten15 reserved inten13 inten12 reserved inten9 inten8 access: r/w reset: 33 16 address: 0055 16 reserved
2-58 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers the usb frame number low register , shown in figure 2-71, contains the lower 8 bits of the 11-bit frame number received from the host. the usb frame number high register , shown in figure 2-72 contains the upper 3 bits of the 11-bit frame number received from the host. figure 2-71. usb frame number low register figure 2-72. usb frame number high register the usb endpoint index register, shown in figure 2-73, identifies the endpoint pair. it serves as an index to endpoint-specific in csr, out csr, in maxp, out maxp and out wrt cnt registers. this register also contains two global bits, iso_upd and auto_fl for endpoints 1-4 regarding the isochronous data transfer. if iso_upd = 0, a data packet in an endpoints in fifo is always ready to transmit upon receiving the next in_token from the host (with matched address & endpoint number). if iso_upd = 1 and the iso bit of the corresponding endpoints in csr is set, then the internal ready to transmit signal to the transmit control logic is delayed until the next sof. in this way the data loaded in frame n will be transmitted out in frame n+1. the iso_upd bit is a global bit for endpoints 1 to 4, and works with isochronous pipes only. if auto_fl = 1, iso_upd = "1", and a particular in endpoints iso bit is set, then at the time the usb fcu detects a sof packet, if the corresponding in endpoints in_pkt_rdy = 1, the usb fcu automatically flushes the oldest packet from the in fifo. in this case, in_pkt_rdy = 1 indicates that two data packet are in the in fifo. since, for iso transfer, double buffering is a requirement, maxp must set to be less than or equal to 1/2 of the fifo size. figure 2-73. usb endpoint index register the endpoint 0 in csr (control & status register), shown in figure 2-74, contains the control and status information of endpoint 0. fn7:0 lower 8 bits of the 11-bit frame number issued with a sof token msb 7 lsb 0 fn7 fn6 fn5 fn4 fn3 fn1 fn0 access: r reset: 00 16 fn2 address: 0056 16 fn10:8 upper 3 bits of the 11-bit frame number issued with a sof token bits 7:3 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved fn9 fn8 access: r reset: 00 16 fn10 address: 0057 16 epindx2:0 endpoint index: bit 2 bit 1 bit 0 0 0 0: function endpoint 0 0 0 1: function endpoint 1 0 1 0: function endpoint 2 0 1 1: function endpoint 3 1 0 0: function endpoint 4 others: unde?ned bits 3:5 reserved (read/write 0) auto_fl auto_flush bit (bit 6) 0: hardware auto fifo ?ush disabled 1: hardware auto fifo ?ush enabled iso_upd iso_update bit (bit 7) 0: iso_update disabled 1: iso_update enabled msb 7 lsb 0 iso_upd auto_fl reserved reserved reserved epindx1 epindx0 access: r/w reset: 00 16 epindx2 address: 0058 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-59 in0csr0 (out_pkt_rdy): the usb fcu sets this bit to a 1 upon receiving a valid setup/out token from the host. the cpu clears this bit after unloading the fifo, by way of writing a 1 to in0csr6. the cpu should not clear the out_pkt_rdy bit before ?nishes decoding the host request. if in0csr2 (send_stall) needs to be set - the cpu decodes an invalid or unsupported request - the setting in0csr6 = 1 & in0csr2 = 1 should be done in a same cpu write. in0csr1 (in_pkt_rdy): the cpu writes a 1 to this bit after finishes writing a packet of data to the endpoint 0 fifo. the usb fcu clears this bit after the packet is successful transmitted to the host, or the in0csr5 (setup_end) bit is set. in0csr2 (send_stall): the cpu writes a 1 to this bit if it decodes an invalid or unsupported standard device request from the host. the usb fcu returns a stall handshake for all subsequent in/out transactions (during control transfer data or status stages) while this bit is set. the cpu writes a 0 to clear this bit. in0csr3 (data_end): for control transfers, the cpu writes a 1 to this bit when it writes (in data phase) or reads (out data phase) the last packet of data from/to the fifo. this bit indicates to the usb fcu that the specific amount of data in the setup phase is transferred. the usb fcu will advance to the status phase once this bit is set. when the status phase completes, the usb fcu clears this bit. when this bit is set to a 1, and the host again requests or sends more data, the usb fcu will return a stall handshake. in0csr4 (force_stall): the usb fcu sets this bit to a 1 if the host sends out a larger data packet than the maxp size, or if during a data stage a command pipe is sent more data or is requested to return more data than was indicated in the setup stage (also see description for in0csr3). the usb fcu returns a stall handshake for all subsequent in/out transactions (during data or status stages) while this bit is set. the cpu writes a 0 to clear this bit. in0csr5 (setup_end): the usb fcu sets this bit to a 1 if a control transfer has ended before the specific length of data is transferred during the data phase. the cpu clears this bit by way of writing a 1 to in0csr7. once the cpu sees the setup_end bit set, it should stop accessing the fifo to service the previous setup transaction. if out_pkt_rdy is set at the same time setup_end is set, it indicates the previous setup transaction ended, and a new setup token is in the fifo. in0csr6 and in0csr7 : these bits are used to clear in0csr0 and in0csr5 respectively. writing a 1 to these bits will clear the corresponding register bit.
2-60 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-74. usb endpoint 0 in csr the usb endpoint x in csr ((control & status register), shown in figure 2-75, contains control and status information of the respective in endpoint 1-4. the specific endpoint is selected by the usb endpoint index register. inxcsr0 (in_pkt_rdy) and inxcsr5 (tx_fifo_not_empty): these two bits are read together to determine in fifo status. a 1 can be written to the inxcsr0 bit by the cpu to indicate a packet of data is written to the fifo (see chapter 2.9.3.1. in (transmit) fifos for detail). inxcsr1 (under_run) this bit is used in iso mode only to indicate to the cpu that a fifo underrun has occurred. the usb fcu sets this bit to a 1 at the beginning of an in token if no data packet is in the fifo. setting this bit will cause the inst12 bit of the interrupt status register 2 to set. the cpu writes a 0 to clear this bit. inxcsr2 (send_stall): the cpu writes a 1 to this bit when the endpoint is stalled (transmitter halt). the usb fcu returns a stall handshake while this bit is set. the cpu writes a 0 to clear this bit. inxcsr3 (iso): the cpu writes a 1 to this bit to initialize the respective endpoint as an isochronous endpoint for in transactions. inxcsr4 (intpt): the cpu writes a 1 to this bit to initialize this endpoint as a status change endpoint for in transactions. this bit is set only if the corresponding endpoint is to be used to communicate rate feedback information (see chapter 2.9.3.1. in (transmit) fifos for details). inxcsr5 (tx_fifo_not_empty): the usb fcu sets this bit to a 1 when there is data in the in fifo. this bit in conjunction with in_pkt_rdy bit will provide the transmit fifo status information (see chapter 2.9.3.1. in (transmit) fifos for details). inxcsr6 (flush): the cpu writes a 1 to this bit to flush the in fifo. if there is one packet in the in fifo, a flush will cause the in fifo to be empty, if there are two packets in the in fifo, a flush will cause the older packet to be flushed out from the in fifo. setting the inxcsr6 (flush) bit during transmission could produce unpredictable results. in0csr0 out_pkt_rdy flag (bit 0) (read only - write 0) 0: out packet is not ready 1: out packet is ready in0csr1 in_pkt_rdy bit (bit 1) (write 1 only or read) 0: in packet is not ready 1: in packet is ready in0csr2 send_stall bit (bit 2) (write 1 only or read) 0: no action 1: stall endpoint 0 by the cpu in0csr3 data_end bit (bit 3) (write 1 only or read) 0: no action 1: last packet of data transferred from/to the fifo in0csr4 force_stall flag (bit 4) (write 0 only or read) 0: no action 1: stall endpoint 0 by the usb fcu in0csr5 setup_end flag (bit 5) (read only - write 0) 0: no action 1: control transfer ended before the speci?c length of data is transferred during the data phase in0csr6 serviced_out_pkt_rdy bit (bit 6) (write only - read 0) 0: no change 1: clear the out_pkt_rdy bit (in0csr0) in0csr7 serviced_setup_end bit (bit 7) (write only - read 0) 0: no change 1: clear the stup_end bit (in0csr5) msb 7 lsb 0 in0csr7 in0csr6 in0csr5 in0csr4 in0csr3 in0csr1 in0csr0 access: r/w reset: 00 16 in0csr2 address: 0059 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-61 inxcsr7 (auto_set): if the cpu sets this bit to a 1, the in_pkt_rdy bit is set automatically by the usb fcu after the number of bytes of data equal to the maximum packet size (maxp) is written into the in fifo (see chapter 2.9.3.1. in (transmit) fifos for details). figure 2-75. usb endpoints x in csr all bits in usb endpoint 0 out csr (control & status register), shown in figure 2-76, are reserved (all control and status info is in endpoint 0 in csr) figure 2-76. usb endpoint 0 out csr the usb endpoint x out csr (control & status register), shown in figure 2-77, contains control and status information of the respective out endpoint 1-4. the specific endpoint is selected by the usb endpoint index register. outxcsr0 (out_pkt_rdy): the usb fcu sets the this bit to a 1 after it successfully receives a packet of data from the host. this bit is cleared by the cpu or by the usb fcu after a packet of data is unloaded from the fifo (see chapter 2.9.3.2. out (receive) fifos for details). outxcsr1 (over_run): this bit is used in iso mode only to indicate to the cpu that a fifo overrun has occurred. the usb fcu sets this bit to a 1 at the beginning of an out token if the outxcsr0 (out_pkt_rdy) bit is not cleared. setting this bit will cause the inst12 bit of the interrupt status register 2 to set. the cpu writes a 0 to clear this bit. outxcsr2 (send_stall): the cpu writes a 1 to this bit when the endpoint is stalled (receiver halt). the usb fcu returns a stall handshake while this bit is set. the cpu writes a 0 to clear this bit. outxcsr3 (iso): the cpu sets this bit to a 1 to initialize the respective endpoint as an isochronous endpoint for out transactions. inxcsr0 in_pkt_rdy bit (bit 0) (write 1 only or read) 0: in packet is not ready 1: in packet is ready inxcsr1 under_run flag (bit 1) (write 0 only or read) 0: no fifo underrun 1: fifo underrun has occurred inxcsr2 send_stall bit (bit 2) 0: no action 1: stall in endpoint x by the cpu inxcsr3 iso bit (bit 3) 0: select non-isochronous transfer 1: select isochronous transfer inxcsr4 intpt bit (bit 4) 0: select non-rate feedback interrupt transfer 1: select rate feedback interrupt transfer inxcsr5 tx_not_ept flag (bit 5) (read only - write 0) 0: transmit fifo is empty 1: transmit fifo is not empty inxcsr6 flush bit (bit 6) (write only - read 0) 0: no action 1: flush the fifo inxcsr7 auto_set bit (bit 7) 0: auto_set disabled 1: auto_set enabled msb 7 lsb 0 inxcsr7 inxcsr6 inxcsr5 inxcsr4 inxcsr3 inxcsr1 inxcsr0 access: r/w reset: 00 16 inxcsr2 address: 0059 16 bits 7:0 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved reserved reserved access: r reset: 00 16 address: 005a 16 reserved
2-62 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers outxcsr4 (force_stall): the usb fcu sets this bit to a 1 if the host sends out a larger data packet than the maxp size. the usb fcu returns a stall handshake while this bit is set. the cpu writes a 0 to clear this bit. outxcsr5 (data_err): the usb fcu sets this bit to a 1 to indicate a crc error or a bit stuffing error received in an iso packet. the cpu writes a 0 to clear this bit. outxcsr6 (flush): the cpu writes a 1 to this to flush the out fifo. if there is one packet in the out fifo, a flush will cause the out fifo to be empty, if there are two packets in the out fifo, a flush will cause the older packet to be flushed out from the out fifo. setting the outxcsr6 (flush) bit during reception could produce unpredictable results. outxcsr7 (auto_clr): if the cpu sets this bit to a 1, the out_pkt_rdy bit is cleared automatically by the usb fcu after the number of bytes of data equal to the maximum packet size (maxp) is unloaded from the out fifo (see chapter 2.9.3.2. out (receive) fifos for details). figure 2-77. usb endpoint x out csr the usb endpoint x in maxp , shown in figure 2-78, indicates the maximum packet size (maxp) of an endpoint x in packet. the default value for endpoint 0 is 8 bytes, the default values for endpoints 1-4 are 0 bytes. the cpu can change this value, as negotiated with the host controller through the set_descriptor command. figure 2-78. usb endpoint x in maxp the usb endpoint x out maxp , shown in figure 2-79, indicates the maximum packet size (maxp) of an endpoint x out packet. the default values for endpoints 1-4 are 0 bytes. the cpu can change this value, as negotiated with the host controller through the set_descriptor command. for endpoint 0, all bits in this register are reserved: endpoint 0 uses in maxp register for both in and out transfers. outxcsr0 out_pkt_rdy flag (bit 0) (write 0 only or read) 0: out packet is not ready 1: out packet is ready outxcsr1 over_run flag (bit 1) (write 0 only or read) 0: no fifo overrun 1: fifo overrun occurred outxcsr2 send_stall bit (bit 2) 0: no action 1: stall out endpoint x by the cpu outxcsr3 iso bit (bit 3) 0: select non-isochronous transfer 1: select isochronous transfer outxcsr4 force_stall flag (bit 4) (write 0 only or read) 0: no action 1: stall endpoint x by the usb fcu outxcsr5 data_err flag (bit 5) (write 0 only or read) 0: no error 1: crc or bit stuf?ng error received in an iso packet outxcsr6 flush bit (bit 6) (write only - read 0) 0: no action 1: flush the fifo outxcsr7 auto_clr bit (bit 7) 0: auto_clr disabled 1: auto_clr enabled msb 7 lsb 0 outxcsr7 outxcsr6 outxcsr5 outxcsr4 outxcsr3 outxcsr1 outxcsr0 access: r/w reset: 00 16 outxcsr2 address: 005a 16 imaxp7:0 maximum packet size (maxp) of endpoint x in packet. maxp = n for endpoints 0, 2, 3, 4 maxp = n * 8 for endpoint 1 n is the value written to this register. for endpoints that support a smaller fifo size, unused bits are not implemented (always write 0 to those bits) msb 7 lsb 0 imaxp7 imaxp6 imaxp5 imaxp4 imaxp3 imaxp1 imaxp0 access: r/w imaxp2 address: 005b 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification universal serial bus 7/9/98 2-63 figure 2-79. usb endpoint x out maxp the usb endpoint x out wrt cnt low & the usb endpoint x out wrt cnt high registers, shown in figure 2-80 and figure 2-81, contain the number of bytes in the endpoint x out fifo. the usb fcu sets the values in these two write count registers after having successfully received a packet of data from the host. the cpu reads these two registers to determine the number of bytes to be read from the fifo. the cpu should read wrt cnt low ?rst then wrt cnt high. figure 2-80. usb endpoint x out wrt cnt low figure 2-81. usb endpoint x out wrt cnt high the usb endpoint x fifo registers , shown in figure 2-82 through figure 2-86, are the usb in (transmit) and out (receive) fifo data registers. the cpu writes data to these registers for the corresponding endpoint in fifo and reads data from these registers for the corresponding endpoint out fifo. figure 2-82. usb endpoint 0 fifo register figure 2-83. usb endpoint 1 fifo register figure 2-84. usb endpoint 2 fifo register omaxp7:0 maximum packet size (maxp) of endpoint x out packet. maxp = n for endpoints 2, 3, 4 maxp = n * 8 for endpoint 1 n is the value written to this register. for endpoints that support a smaller fifo size, unused bits are not implemented (always write 0 to those bits) msb 7 lsb 0 omaxp7 omaxp6 omaxp5 omaxp4 omaxp3 omaxp1 omaxp0 access: r/w omaxp2 address: 005c 16 w_cnt7:0 byte count. this register contains the lower 8 bits of the byte count register msb 7 lsb 0 w_cnt7 w_cnt6 w_cnt5 w_cnt4 w_cnt3 w_cnt1 w_cnt0 access: r reset: 00 16 w_cnt2 address: 005d 16 w_cnt9:8 byte count. this register contains the upper 2 bits of the byte count register bits 7:2 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved w_cnt9 w_cnt8 access: r reset: 00 16 address: 005e 16 reserved data_7:0 endpoint 0 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0060 16 data_7:0 endpoint 1 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0061 16 data_7:0 endpoint 2 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0062 16
2-64 7/9/98 universal serial bus 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-85. usb endpoint 3 fifo register figure 2-86. usb endpoint 4 fifo register data_7:0 endpoint 3 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0063 16 data_7:0 endpoint 4 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0064 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification master cpu bus interface 7/9/98 2-65 2.10 master cpu bus interface this device has a bus interface function with 2 i/o buffers that can be operated in slave mode by control signals from the master cpu (see figure 2-87. bus interface circuit). the bus interface can be connected directly to either a r/ w type of cpu or a cpu with rd and wr separate signals. slave mode is selected with the bit 7 of the data buffer control register 0. the single data bus buffer mode and the double data bus buffer mode are selected with bit 7 of the data bus buffer control register 1. when selecting the double data bus buffer mode, port p7 2 becomes s 1 input. prior to enabling the mbi, port 6 must be placed in input mode by writing 00 16 to p6d (0015 16 ). figure 2-87. bus interface circuit when data is written to the mcu from the master cpu, an input buffer full interrupt request occurs. similarly, when data is read from the master cpu, an output buffer empty interrupt request occurs. address description acronym and value at reset 0048 16 data bus buffer register 0 dbb0=00 0049 16 data bus buffer status register 0 dbbs0=00 004a 16 data bus buffer control register 0 dbbc0=00 004c 16 data bus buffer register 1 dbb1=00 004d 16 data bus buffer status register 1 dbbs1=00 004e 16 data bus buffer control register 1 dbbc1=00 pin description pin description p6 0 -p6 7 are multiplexed with dq0-dq7 p5 6 is multiplexed with r or e p5 2 is multiplexed with obf 0 p5 7 is multiplexed with w or r/ w p5 3 is multiplexed with ibf 0 p7 2 is multiplexed with s 1 p5 4 is multiplexed with s 0 p7 3 is multiplexed with ibf 1 p5 5 is multiplexed with a 0 p7 4 is multiplexed with obf 1 data bus input data bus buffer 0 output data bus buffer 0 u 7 u 6 u 5 u 4 a 00 u 2 ibf 0 b 7 b 0 system bus obf 0 b 1 b 0 data bus buffer control register 0 obf 0 ibf 0 a 0 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 s 0 r w rd wr dbb 0 dbbs 0 input data bus buffer 1 output data bus buffer 1 u 7 u 6 u 5 u 4 a 01 u 2 ibf 1 b 7 b 0 obf 1 b 1 b 0 data bus buffer control register 1 obf 1 ibf 1 a 0 s 1 r w rd wr dbb 1 dbbs 1
2-66 7/9/98 master cpu bus interface 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers when the bus interface is operating, dq 0 -dq 7 become a 3-state data bus that sends and receives data, command, and status to and from the master cpu. at the same time, w, r, s 0 , s 1 , and a 0 become host cpu control signal input pins. the two input buffer full interrupt requests and two output buffer full requests are multiplexed as shown in figure 2-88. the bus interface can be operated under normal mcu control or under on-chip dma control for fast data transfer. if a master cpu has a large amount of data to be transferred, use of the on-chip dma controller is highly recommended. the bus interface signal input level can be programmed as cmos level (default) or as ttl level. bit 7 of the port control register (ptc7) is used for the input level selection. figure 2-88. data bus buffer interrupt request circuit figure 2-89. data bus buffer status register 0 one-shot pulse generating circuit one-shot pulse generating circuit one-shot pulse generating circuit one-shot pulse generating circuit rising edge detection circuit rising edge detection circuit rising edge detection circuit rising edge detection circuit input buffer full interrupt request signal ibf output buffer empty interrupt request signal obe input buffer full ?ag 0 ibf0 input buffer full ?ag 1 ibf1 output buffer full ?ag 0 obf0 output buffer full ?ag 1 obf1 set interrupt request at this rising edge set interrupt request at this rising edge ibf0 ibf1 ibf obf1 obe (obe1) obf0 (obe0) dbbs00 output buffer full (obf 0 ) flag (bit 0) 0: output buffer empty. 1: output buffer full. dbbs01 input buffer full (ibf 0 ) flag (bit 1) 0: input buffer empty. 1: input buffer full. dbbs02 user de?nable (u2) flag (bit 2) dbbs03 a 0 (a 00 ) flag (bit 3) indicates the a 0 status when ibf ?ag is set dbbs04 user de?nable (u4) flag (bit 4) dbbs05 user de?nable (u5) flag (bit 5) dbbs06 user de?nable (u6) flag (bit 6) dbbs07 user de?nable (u7) flag (bit 7) msb 7 lsb 0 dbbs06 dbb05 dbbs04 dbbs03 dbbs01 dbbs00 access: r/w reset: 00 16 dbbs02 dbbs07 address: 0049 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification master cpu bus interface 7/9/98 2-67 figure 2-90. data bus buffer control register 0 figure 2-91. data bus buffer status register 1 figure 2-92. data bus buffer control register 1 dbbc00 obf output selection bit (bit 0) 0: p5 2 pin is operated as gpio 1: p5 2 pin is operated as obf 0 output pin dbbc01 ibf output selection bit (bit 1) 0: p5 3 pin is operated as gpio 1: p5 3 pin is operated as ibf 0 output pin dbbc02 ibf 0 interrupt selection bit (bit 2) 0: ibf 0 interrupt is generated by both write-data (a 0 = 0) and write-command (a 0 = 1) 1: ibf 0 interrupt is generated by write-command (a 0 = 1) only dbbc03 output buffer 0 empty interrupt disable bit (bit 3) 0: enabled 1: disabled dbbc04 input buffer 0 full interrupt disable bit (bit 4) 0: enabled 1: disabled dbbc05 reserved (read/write 0) dbbc06 master cpu bus interface enable bit (bit 6) 0: p6 0 -p6 7 , p5 4 -p5 7 are gpio pins 1: p6 0 -p6 7 , p5 4 -p5 7 are bus interface signals dq0-dq7, s 0 , a 0 , r, w respectively. dbbc07 bus interface type selection bit (bit 7) 0: rd, wr separate type bus 1: r/w type bus. msb 7 lsb 0 dbbc06 dbbc01 dbbc00 access: r/w reset: 00 16 dbbc02 dbbc07 address: 004a 16 dbbc03 dbbc04 reserved msb 7 lsb 0 dbbs16 dbb15 dbbs14 dbbs13 dbbs11 dbbs10 dbbs10 output buffer full (obf 1 ) flag (bit 0) 0: output buffer empty. 1: output buffer full. dbbs11 input buffer full (ibf 1 ) flag (bit 1) 0: input buffer empty. 1: input buffer full. dbbs12 user de?nable (u2) flag (bit 3) dbbs13 a 0 (a 01 ) flag (bit 2) indicates the a 0 status when ibf ?ag is set dbbs14 user de?nable (u4) flag (bit 4) dbbs15 user de?nable (u5) flag (bit 5) dbbs16 user de?nable (u6) flag (bit 6) dbbs17 user de?nable (u7) flag (bit 7) access: r/w reset: 00 16 dbbs12 dbbs17 address: 004d 16 dbbc10 obf 1 output selection bit (bit 0) 0: p7 4 pin is operated as gpio 1: p7 4 pin is operated as obf 1 output pin if dbbc17 = 1 dbbc11 ibf 1 output selection bit (bit 1) 0: p7 3 pin is operated as gpio 1: p7 3 pin is operated as ibf 1 output pin if dbbc17 = 1 dbbc12 ibf 1 interrupt selection bit (bit 2) 0: ibf 1 interrupt is generated by both write-data (a 0 = 0) and write-command (a 0 = 1) 1: ibf 1 interrupt is generated by write-command (a 0 = 1) only dbbc13 output buffer 1 empty interrupt disable bit (bit 3) 0: enabled 1: disabled dbbc14 input buffer 1 full interrupt disable bit (bit 4) 0: enabled 1: disabled dbbc15 reserved (read/write 0) dbbc16 reserved (read/write 0) dbbc17 data bus buffer function selection bit (bit 7) 0: single data bus buffer - p7 2 is used as gpio 1: double data bus buffer - p7 2 is used as s 1 input msb 7 lsb 0 dbbc11 dbbc10 access: r/w reset: 00 16 dbbc12 dbbc17 address: 004e 16 reserved dbbc13 dbbc14 reserved
2-68 7/9/98 master cpu bus interface 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.10.1 data bus buffer status registers (dbbs0, dbbs1) the data bus buffer status register is an 8-bit register that indicates the data bus status, with bits 0, 1, and 3 being dedicated read-only bits. bits 2, 4, 5, 6, and 7 are user de?nable ?ags set by software, and can be read and write. when the a 0 pin is high, the master cpu can read the contents of this register. output buffer full flag (obf 0 , obf 1 ) the obf 0 and the obf 1 flags are set high when data is written to the output data bus buffer by the slave cpu and is cleared to 0 when data is read by the master cpu. input buffer full flag (ibf 0 , ibf 1 ) the ibf 0 and the ibf 1 flags are set high when data is written to the input data bus buffer by the master cpu and is cleared to 0 when data is read by the slave cpu. a 0 flag (a 00 , a 01 ) the level of the a 0 pin is latched when data has been written from the host cpu to the input data bus buffer. 2.10.2 input data bus buffer registers (dbbin 0 , dbbin 1 ) the data on the data bus is latched into dbbin 0 or dbbin 1 by a write request from the master cpu. the data in dbbin 0 or dbbin 1 can be read from the data bus buffer register in the sfr area. 2.10.3 output data bus buffer registers (dbbout 0 , dbbout 1 ) data is set in dbbout 0 or dbbout 1 by writing to the data bus buffer register in the sfr area. when the a 0 pin is low, the data of this register is output by a read request from the host cpu.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification direct memory access controller 7/9/98 2-69 2.11 direct memory access controller this device contains a two-channel direct memory access controller (dmac). each channel performs fast data transfers between any two locations in the memory map initiated by specific peripheral events or software triggers. the main features of the dmac are as follows: ? two independent channels ? single-byte and burst transfer modes ? 16-bit source and destination address registers (for a 64k byte address space) ? 16-bit transfer count registers (for up to 64k bytes transferred before under?ow) ? source/destination register automatic increment/decrement and no-change options ? source/destination/transfer count register reload on write or after transfer count register under?ow options ? transfer requests from usb (9), mbi (4), external interrupts (4), uart1 (2), uart2 (2), sio (1), timerx (1), timery (1), timer1 (1), and software triggers ? closely coupled with usb and mbi for ef?cient data transfers ? interrupt generated for each channel when their respective transfer count register under?ows ? fixed channel priority (channel 0 > channel 1) ? two cycles of f required per byte transferred each channel of the dmac is made up of the following: ? 16-bit source and destination registers ? a 16-bit transfer count register ? two mode registers ? status ?ags contained in a status register shared by the two channels ? control and timing logic address description acronym and value at reset 003f 16 dmac index and status register dmais=00 0040 16 dmac channel x mode register 1 dmaxm1=00 0041 16 dmac channel x mode register 2 dmaxm2=00 0042 16 dmac channel x source register low dmaxsl=00 0043 16 dmac channel x source register high dmaxsh=00 0044 16 dmac channel x destination register low dmaxdl=00 0045 16 dmac channel x destination register high dmaxdh=00 0046 16 dmac channel x transfer count register low dmaxcl=00 0047 16 dmac channel x transfer count register high dmaxch=00
2-70 7/9/98 direct memory access controller 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers the 16-bit source and destination registers allow accesses to any two locations in the 64k byte memory area. the 16-bit transfer count register decrements by one for each transfer performed and causes an interrupt and flag to be set when it underflows. the mode registers control the configuration and operation of the dmac channel associated with the registers. a block diagram of the dmac is shown in figure 2-93. the sfr addresses for the two mode, source, destination, and transfer count registers of a channel are the same for each channel. which channels registers are accessible is determined by the value of the dmac channel index bit (dci) (bit 7 of the dmac index and status register (dmais)). when this bit is a 0, channel 0 registers are accessible, and when this bit is a 1, channel 1 registers are accessible. the configuration of dmais and the mode registers are shown in figure 2-94, figure 2-95, figure 2-96, and figure 2-97. figure 2-93. dmac block diagram 2.11.1 operation each channel of the dmac transfers byte data from a source address to a destination address when a selected event occurs. if single-byte transfer mode is enabled, one byte of data is transferred per request. if burst transfer mode is enabled, several bytes can be transferred per request, one byte at a time. a temporary register internal to the dmac stores the data read from the source address until it is written to the destination address on the next cycle. the transfer of one byte takes two cycles of f and causes the cpu and possibly the other dmac channel to stall during this time. at least one cycle of f with the cpu operating must take place between transfers by the same dmac channel caused by different events or between transfers by the two dmac channels. the dmac does not operate during wit, stp, or hold states. 0 15 mode reg 1 mode reg 2 temp reg ch 0 count latch data bus ch 0 timing generator address bus interrupts: uart1 rx & tx, sio, extint0, (d0cen; d0crr; (d0srce, d0srid, (d0drce. d0drid, dmac ch 0 (d0dwc) (d0dwc) (d0dwc) 0 15 int detect, i-?ag ch 0 destination latch ch 0 destination reg 0 15 ch 0 source latch ch 0 source reg (d0tms) d0umie; d0swt; d0hrs3,2,1,0) (d0uf) interrupt dmac channel 0 dmac channel 1 index & data bus status reg signals: obe0, ibf0(data), ep1, ep2, ep3 out_pkt_rdy or int detect, i-?ag interrupts: uart2 rx & tx, extint1, signals: obe1, ibf1(data), ep1, ep2, timer1, timerx, cntr0 ep4 out_pkt_rdy or (d0uf, d0sfi) (d1uf, d1sfi) ch 0 count reg timery, cntr1 ep1 out_fifo_not_empty ep1 out_fifo_not_empty d0rld) d0rld) (d0daue) int gen (dtsc) (drldd) (drldd) in_pkt_rdy, in_pkt_rdy,
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification direct memory access controller 7/9/98 2-71 2.11.1.1 source, destination, and transfer count register operation the user can choose whether the source and destination register for each channel will increment by one, decrement by one, or remain unchanged after each transfer by setting bits 0 through 3 (dxsrid, dxsrce, dxdrid, and dxdrce) of dmac channel x mode register 1 (dmaxm1) to the appropriate values. the values in the source and destination registers are updated with their reload latch values when the transfer count register underflows. the transfer count register is also reloaded when it underflows, and both a flag (dxuf) and the dmac interrupt associated with the channel are set. reload of the source and destination registers due to underflow of the transfer count register can be disabled by setting to 1 the dmac register reload disable bit (drldd). this bit affects reload for both channel 0 and channel 1. because the transfer count register is 16-bits wide, up to 65,536 transfers can take place before an underflow and the resulting actions described above occur. if the channel x disable after count register underflow enable bit (dxdaue) is set to a 1, then the channel x enable bit (dxcen) is cleared to a 0 when the transfer count register underflows, disabling channel x of the dmac. the source, destination, and transfer count registers of a dmac channel can be updated with their reload latch value at any time by setting to a 1 the dmac channel x register reload bit (dxrld). dmac source, destination, and transfer count register read and write method read and write operations on the high and low-order bytes of the source, destination, and transfer count registers must be performed in a specific order. write method when writing to the source, destination, or transfer count register, the low-order byte is written first. next, the high-order byte is written. when this is done, the data is placed in the reload latch of the high-order byte of the register and the previously written low-order byte data is placed in the reload latch of the low-order byte. at this point, if the dmac channel x write control bit (dxdwc) is 0, the values in the reload latches are also loaded in the low and high-order bytes of the register. if dxdwc is 1, the data in the reload latches are loaded in the register after the transfer count register of the dmac channel underflows or the dxrld bit of the dmac channel is set to a 1. read method when reading from the source, destination, or transfer count register, the high-order byte is read first. the low-order byte of the register is then read. the value read from the low-order byte of the register is its value when the high-order byte was read. 2.11.1.2 dmac transfer request sources the hardware source for initiating a dmac transfer for each channel is selectable by setting the dmac channel x hardware transfer request source bits (dxhrs0, 1, 2, 3) to appropriate values. the choices for channel 0 are the uart1 receive or transmit interrupts, the timery interrupt, external interrupt 0, one of three usb endpoint out_pkt_rdy signals, one of three usb endpoint in_pkt_rdy signals, the usb endpoint 1 out_fifo_not_empty signal, the obe0 and ibf0 (data) signals from the mbi, the sio combined receive/transmit interrupt, and the cntr1 interrupt. the choices for channel 1 are the uart2 receive and transmit interrupts, the timerx interrupt, external interrupt 1, one of three usb endpoint out_pkt_rdy signals, one of three usb endpoint in_pkt_rdy signals, the usb endpoint 1 out_fifo_not_empty signal, the obe1 and ibf1 (data) signals from the mbi, the timer1 interrupt, and the cntr0 interrupt.
2-72 7/9/98 direct memory access controller 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers in addition, each channel has a software trigger that can initiate a dmac transfer. the software trigger is set by writing a 1 to the dmac software transfer trigger (dxswt). the hardware transfer request source for each channel can be disabled by writing a 0 to dxhrs0, 1, 2, and 3. when these bits are all 0, which is the reset state, only the software trigger can be used to initiate a transfer. the initiating source for each channel is latched by the dmac asynchronously and sampled on the rising edge of f . writing a 1 to the dmac channel x transfer initiation source capture register reset bit (dxcrr) causes the initiating source sample latch of the associated dmac channel to be reset. the sample latch is reset automatically one cycle of f after a transfer request is detected. new transfer requests for a channel that occur during a dmac transfer by that same channel are latched as long as they occur after the sample latch is reset. however, if multiple transfer requests occur during a transfer, only one transfer request will be registered. if an interrupt is chosen as the initiating source for dmac transfers, its interrupt control bit located in one of the three interrupt control registers of the icu should be cleared to 0 if the user does not wish to have the interrupt serviced by the cpu. 2.11.1.3 transfer features for usb and mbi in order to make the transfer of data between the usb endpoint fifos and the input and output buffers of the mbi more efficient, special features have been included in the transfer request logic of each dmac channel. these features are enabled for a channel when one of the usb endpoint signals is selected as the hardware transfer request source and the dmac channel x usb and mbi enable bit (dxumie) is set to a 1. these features are only intended to be used with single-byte transfer mode. usb out fifo to mbi output buffer transfers the special features provided by both dmac channels for transfer of data from a usb out fifo to one of the mbi output buffers help facilitate either packet-by-packet transfers or byte-by-byte transfers. packet-by-packet transfers when a usb endpoint out_pkt_rdy signal is selected as the hardware transfer request source for a dmac channel and the dxumie bit of the same channel is set to a 1, a transfer request is generated for that dmac channel when the out_pkt_rdy signal for the chosen usb endpoint is high and output buffer x (where x is 0 for dmac channel 0 and 1 for dmac channel 1) of the mbi is empty. the out_pkt_rdy signal remains high until all bytes of the packet have been read from the out fifo corresponding to that endpoint. thus, the first transfer request is generated when the out_pkt_rdy signal goes high and subsequent transfer requests are generated each time output buffer x becomes empty. once the final byte of the received packet has been read, the out_pkt_rdy signal automatically goes low (if this option is enabled in the usb block). this in turn causes the source, destination, and transfer count registers of the involved dmac channel to be reloaded (unless the drldd bit is set to a 1) and the dmac interrupt for the involved channel to be set. in addition, if the dxdaue bit associated with the channel is 1, the channels dxcen bit is automatically cleared to 0, disabling the channel. this feature allows a channel of the dmac in single-byte transfer mode to automatically transfer a received packet of an endpoint from the endpoints out fifo to the master cpu (via the mbi) without any intervention by the on-chip cpu. also, because the source, destination, and transfer count registers are automatically reloaded once the current packet has been completely transferred, on-chip cpu intervention is not needed to set up the dmac channel for transfer of subsequently received packets, even in the case of reception of a short packet.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification direct memory access controller 7/9/98 2-73 in order for this mode to function correctly, the time from the dmac writing data to mbi output buffer x (which causes pin obfx to go high) until the end of a master read of mbi output buffer x) must be greater than 104.167*(3 - (12e6/ f ))ns. for example, if f = 12mhz, the delay must be greater than 208.334ns, and if f = 6mhz, the delay must be greater than 104.167ns. when f is less than or equal to 4mhz, no delay is required. byte-by-byte transfers when the usb endpoint 1 out_fifo_not_empty signal is chosen as the hardware transfer request source for a dmac channel and the dxumie bit of the same channel is set to a 1, a transfer request is generated for the dmac channel if the endpoint 1 out fifo is not empty and output buffer x of the mbi is empty. thus, a transfer request is generated as soon as new data is received in the endpoint 1 out fifo and the master cpu has read the data previously placed in mbi output buffer x. as is the case when the packet-by-packet method is used, the out_pkt_rdy signal goes high once a complete packet has been received. it remains high until all bytes of the packet have been read from the out fifo. when the final byte has been read from the out fifo, the out_pkt_rdy signal goes low (if this option is enabled in the usb block), which causes the source, destination, and transfer count registers of the involved dmac channel to be reloaded (unless the drldd bit is set to a 1) and the dmac interrupt corresponding to the involved channel to be set. also, if the dxdaue bit associated with the channel is 1, the channels dxcen bit is automatically cleared to 0, disabling the channel. if the last byte of the packet has been read from the out fifo before the end_of_packet signal is received by the usb block, the out_pkt_rdy signal will still go high and then low a short period of time later (if this option is enabled in the usb block). this feature allows a channel of the dmac in single-byte transfer mode to automatically transfer data received for endpoint 1 from the endpoint 1 out fifo to the master cpu (via the mbi) prior to reception of the complete packet. mbi input buffer to usb in fifo transfers when a usb endpoint in_pkt_rdy signal is selected as the hardware transfer request source for a dmac channel and the dxumie bit of the same channel is set to a 1, a transfer request is generated when the in fifo associated with the endpoint is not full (with respect to the programmed packet size) and input buffer x of the mbi contains data. the transfer request is not generated if input buffer x contains a command. the in fifo associated with an endpoint is not full when in_pkt_rdy is low. the in_pkt_rdy signal remains low until a full packet has been written to the in fifo. thus, the first transfer request is generated when the in_pkt_rdy goes low and subsequent transfer requests are generated when data is written to input buffer x by an external device. once the full packet has been written to the in fifo, the in_pkt_rdy signal is automatically set to a 1 (assuming this option is enabled in the usb block). in this case, the source, destination, and transfer count registers are not automatically reloaded. instead, the packet size for the endpoint should be written to the transfer count register at initialization time so that it underflows and reloads the registers once the last byte of the data is transferred from input buffer x to the endpoints in fifo. the feature described above allows a channel of the dmac, in single-byte transfer mode, to automatically transfer data received from the master cpu (via the mbi) to the endpoints in fifo without any intervention by the on-chip cpu. additionally, since the in_pkt_rdy signal associated with the endpoint is automatically set (assuming this option is enabled in the usb block), multiple packets can be transferred by a channel of the dmac without on-chip cpu intervention. note however that short packets are not handled automatically and instead require intervention by the on- chip cpu.
2-74 7/9/98 direct memory access controller 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.11.1.4 dmac transfer mode each channel of the dmac can be operated in single-byte transfer mode or burst transfer mode. the choice is made by the setting of the channel x dmac transfer mode selection bit (dxtms). when single-byte transfer mode is selected, one byte of data is transferred per transfer request. when burst transfer mode is selected, the value in the transfer count register determines how many single byte transfers occur per transfer request. for example, if the value in the transfer count register is 0014 16 , 21 transfers will occur before control of the address bus and data bus is given back to the cpu. 2.11.1.5 dmac transfer timing a dmac transfer can occur at any point during the execution of an instruction by the cpu. however, at least one cycle of f with the cpu operating takes place between transfers by the same dmac channel caused by different events or between transfers by the two dmac channels. also, burst transfers and possibly single-byte transfers are prevented from occurring during interrupt service routines. the transfer initiating sources for the two channels are latched by the dmac asynchronously and polled on the rising edge of f . if a transfer request is seen for both channels, the channel 0 request will be serviced first followed by the channel 1 request. if channel 1 is performing a burst transfer when channel 0 receives a transfer request, the channel 1 transfer is suspended at the end of the next source read/destination write operation. the channel 0 transfer is then serviced. once the channel 0 transfer completes, the channel 1 transfer automatically continues where it left off. in order to prevent channel 0 from completely shutting out channel 1 transfers, one cycle of a suspended channel 1 transfer is allowed to occur after a channel 0 burst transfer even if another channel 0 transfer request is pending. if the i flag value is 0 and an interrupt with its interrupt control bit set to a 1 occurs during a burst transfer by either channel, the transfer is suspended, allowing the interrupt service routine to be entered. the dmac channel x suspend (due to interrupt service request) flag (dxsfi) corresponding to the channel whose transfer was suspended is automatically set to a 1 at this time. when the i flag value (which was automatically set to a 1 when the interrupt service routine was entered) becomes a 0 again, the dxsf flag is automatically cleared and the transfer continues where it left off. if a dmac burst transfer request occurs during the servicing of an interrupt, the transfer does not take place until after the interrupt has been serviced, which is understood to have happened when the i flag becomes a 0. if the dmac transfer suspend control bit (dtsc) is set to a 1, both single-byte and burst mode transfers are suspended by interrupts. a suspended dmac transfer can be re-started in the interrupt service routine by writing a 1 to the dxcen bit of the suspended channel. sample timing diagrams are shown in figure 2-98, figure 2-99, and figure 2-100. for a single-byte transfer initiated by a hardware source, a single-byte transfer initiated by the software trigger, and a burst transfer initiated by a hardware source, respectively.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification direct memory access controller 7/9/98 2-75 figure 2-94. dmais con?guration figure 2-95. dmaxm1 con?guration d0uf dmac channel 0 count register under?ow flag (bit 0) 0: channel 0 transfer count register under?ow has not occurred 1: channel 0 transfer count register under?ow has occurred d0sfi dmac channel 0 suspend (due to interrupt service request) flag (bit 1) 0: channel 0 transfer has not been suspended 1: channel 0 transfer has been suspended d1uf dmac channel 1 count register under?ow flag (bit 2) 0: channel 1 transfer count register under?ow has not occurred 1: channel 1 transfer count register under?ow has occurred d1sfi dmac channel 1 suspend (due to interrupt service request) flag (bit 3) 0: channel 1 transfer has not been suspended 1: channel 1 transfer has been suspended dtsc dmac transfer suspend control bit (bit 4) 0: only burst transfers are suspended during interrupt servicing 1: both burst and single-byte transfers are suspended during interrupt servicing drldd dmac register reload disable bit (bit 5) 0: reload of source and destination registers of both channels enabled 1: reload of source and destination registers of both channels disabled bit 6 reserved (read/write 0) dci channel index bit (bit 7) 0: channel 0 mode, source, destination, and transfer count registers accessible 1: channel 1 mode, source, destination, and transfer count registers accessible msb 7 lsb 0 dci reserved drldd dtsc d1sfi d1uf d0sfi d0uf access: r/w reset: 00 16 address: 003f 16 msb 7 lsb 0 dxtms dxrld dxdaue dxdwc dxdrce dxdrid dxsrce dxsrid dxsrid dmac channel x source register increment/decrement select bit (bit 0) 0: increment after transfer 1: decrement after transfer dxsrce dmac channel x source register increment/decrement enable bit (bit 1) 0: increment/decrement disabled (no change after transfer) 1: increment/decrement enabled dxdrid dmac channel x destination register increment/decrement select bit (bit 2) 0: increment after transfer 1: decrement after transfer dxdrce dmac channel x destination register increment/decrement enable bit (bit 3) 0: increment/decrement disabled (no change after transfer) 1: increment/decrement enabled dxdwc dmac channel x data write control bit (bit 4) 0: write data in reload latches and registers 1: write data in reload latches only dxdaue dmac channel x disable after count register under?ow enable bit (bit 5) 0: channel x not disabled after count register under?ow 1: channel x disabled after count register under?ow dxrld dmac channel x register reload bit (bit 6) 0: no action (bit is always read as 0) 1: setting to 1 causes the source, destination, and transfer count registers of channel x to be reloaded dxtms dmac channel x transfer mode selection bit (bit 7) 0: single-byte transfer mode 1: burst transfer mode access: r/w reset: 00 16 address: 0040 16
2-76 7/9/98 direct memory access controller 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-96. dma0m2 con?guration figure 2-97. dma1m2 con?guration msb 7 lsb 0 d0cen d0crr d0umie d0swt d0hrs3 d0hrs2 d0hrs1 d0hrs0 d0hrs3,2,1,0 dmac channel 0 hardware transfer request source bits (bits 3, 2, 1, 0) 0000: disabled 0001: uart1 receive interrupt 0010: uart1 transmit interrupt 0011: timery interrupt 0100: external interrupt 0 0101: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0110: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0111: usb endpoint 3 in_pkt_rdy signal (falling edge active) 1000: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1001: usb endpoint 1 out_fifo_not_empty signal (rising edge active) 1010: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1011: usb endpoint 3 out_pkt_rdy signal (rising edge active) 1100: mbi obe 0 signal (rising edge active) 1101: mbi ibf 0 (data) signal (rising edge active) 1110: sio receive/transmit interrupt 1111: cntr1 interrupt d0swt dmac channel 0 software transfer trigger (bit 4) 0: no action (bit is always read as 0) 1: writing 1 requests a channel 0 transfer d0umie dmac channel 0 usb and mbi enable bit (bit 5) 0: disabled 1: enabled d0crr dmac channel 0 transfer initiation source capture register reset (bit 6) 0: no action (bit is always read as 0) 1: setting to 1 causes reset of the channel 0 capture register d0cen dmac channel 0 enable bit (bit 7) 0: channel 0 disabled 1: channel 0 enabled access: r/w reset: 00 16 address: 0041 16 d1hrs3,2,1,0 dmac channel 1hardware transfer request source bits (bits 3, 2, 1, 0) 0000: disabled 0001: uart2 receive interrupt 0010: uart2 transmit interrupt 0011: timerx interrupt 0100: external interrupt 1 0101: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0110: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0111: usb endpoint 4 in_pkt_rdy signal (falling edge active) 1000: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1001: usb endpoint 1 out_fifo_not_empty signal(rising edge active) 1010: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1011: usb endpoint 4 out_pkt_rdy signal (rising edge active) 1100: mbi obe1 signal (rising edge active) 1101: mbi ibf1(data) signal (rising edge active) 1110: timer1 interrupt 1111: cntr0 interrupt d1swt dmac channel 1 software transfer trigger (bit 4) 0: no action (bit is always read as 0) 1: writing 1 requests a channel 0 transfer d1umie dmac channel 1 usb and mbi enable bit (bit 5) 0: disabled 1: enabled d1crr dmac channel 1 transfer initiation source capture register reset (bit 6) 0: no action (bit is always read as 0) 1: setting to 1 causes reset of the channel 1 capture register d1cen dmac channel 1 enable bit (bit 7) 0: channel 1 disabled 1: channel 1 enabled msb 7 lsb 0 d1cen d1crr d1umie d1swt d1hrs3 d1hrs2 d1hrs1 d1hrs0 access: r/w reset: 00 16 address: 0041 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification direct memory access controller 7/9/98 2-77 figure 2-98. dmac transfer - hardware source initiated figure 2-99. dmac transfer - software trigger initiated f out sync out rd wr address data a5 adl1 data 85 dma data dma data adl2 adl2, 00 dma dest. dma source pc + 2 adl1, 00 pc + 1 pc pc + 3 opcode3 address address pc + 4 lda$zz sta $zz (first cycle) dmac transfer sta $zz (last 2 cycles) data dmac transfer signal (port3 3 ) transfer request source (active low) source sampling transfer request source sample latch reset transfer request next inst. 3c 18 41 90 opcode2 dma data opcode3 dma dest. dma source 42,00 pc + 2 pc + 1 pc pc + 3 opcode5 address address pc + 4 ldm #$90, $41 single cycle dmac transfer inst. next inst. pc + 6 dma data f out sync out rd wr address data dmac transfer signal (port3 3 ) transfer request source (active low) source sampling transfer request source sample latch reset transfer request opcode4 pc + 5 single cycle inst. single cycle inst.
2-78 7/9/98 direct memory access controller 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-100. dmac transfer - burst transfer mode a5 adl1 data 85 dma data1 dma data1 dma data2 dma dest. dma source pc + 2 adl1, 00 pc + 1 pc adl2 address1 address1 pc + 3 lda $zz sta $zz (first cycle) dmac transfer sta $zz (second cycle) dma data2 dma source address2 address2 dma dest. f out sync out rd wr address data dmac transfer signal (port3 3 ) transfer request source (active low) source sampling transfer request source sample latch reset transfer request
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification special count source generator 7/9/98 2-79 2.12 special count source generator this device has a built-in special count source generator. it consists of two 8-bit timers: scsg1, and scsg2 (see figure 2-101.) the contents of the timer latch, corresponding to each timer, determine the divide ratio. the timers can be written to at any time. the output of the special count source generator can be a clock source for timer x, sio and the two uarts. figure 2-101. scsg block diagram 2.12.1 scsg operation the scsg1 and scsg2 are both down count timers. when the count of a timer reaches 00 16 , an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are loaded into the timer. for the count operation for scsg1 with the data write mode set to write to the latch only see (figure 2-102.). a memory map and the initial values after reset of the timers and timer reload latches are detailed above. the divide ratio of each timer is given by 1/( n + 1), where n is the value written to the timer. the output of the first timer (scsg1) is effectively anded with the original clock ( f ) to provide a count source for the second timer (scsg2). this results in a count source of n /( n + 1) being fed to scsg2. the output of the scsg is a clock, scsgclk . the frequency is calculated as follows: where scsg1 is the value written to scsg1 and scsg2 is the value written to scsg2. address description acronym and value at reset 002d 16 special count source generator1 scsg1=ff 002e 16 special count source generator2 scsg2=ff 002f 16 special count source mode register scsm=00 f scsgm1 scsgm3 scsg1 reload latch (8) scsg1 (8) scsgm1 scsgm1 scsgm3 scsgm0 scsgm2 scsg2 reload latch (8) scsgm3 scsgclk (to uarts, timer x and sio) scsg2 (8) scsgclk f scsg 1 scsg 11 + --------------------------- - 1 scsg 21 + --------------------------- - =
2-80 7/9/98 special count source generator 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-102. timer count operation for scsg1 2.12.2 scsg description 2.12.2.1 scsg1 scsg1 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer. write method when writing to the timer, the data is placed in the scsg1 reload latch. at this point, if the scsg1 data write control bit (scsgm0) is 0, the value in the scsg1 reload latch is also loaded in scsg1. if scsgm0 is 1, the data in the scsg1 reload latch is loaded in scsg1 after scsg1 underflows. scsg1 count stop control if the scsg1 count stop bit (scsgm1) (bit 1 of the scsgm register) is set to a 1, scsg1 stops counting. this allows f to bypass scsg1 and act as the clock source for scsg2. if the scsgclk output control bit (scsgm3) is cleared to 0, scsgclk is disabled and scsg1 stops counting (see figure 2-103.). 2.12.2.2 scsg2 scsg2 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer. write method when writing to the timer, the data is placed in the scsg2 reload latch. at this point, if the scsg2 data write control bit (scsgm2) is low, the value in the scsg2 reload latch is also loaded in scsg2. if scsgm2 is high, the data in the scsg2 reload latch is loaded in scsg2 after scsg2 underflows. figure 2-103. scsgm register count source scsg1 contents scsg1 under?ow scsg1 latch contents scsg1 reload latch contents loaded into scsg1 10 nn -1 1 0 m m-1 n m msb 7 lsb 0 scsgm3 scsgm1 scsgm0 scsgm0 scsg1 data write control bit (bit 0) 0: write data in latch and timer 1: write data in latch only scsgm1 scsg1 count stop bit (bit 1) 0: count start 1: count stop scsgm2 scsg2 data write control bit (bit 2) 0: write data in latch and timer 1: write data in latch only scsgm3 scsgclk output control bit (bit 3) 0: scsgclk output disabled (scsg1 and scsg2 off) 1: scsgclk output enabled. bits 4-7 reserved (read/write 0) access: r/w reset: 00 16 scsgm2 address: 002f 16 reserved reserved reserved reserved
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification special count source generator 7/9/98 2-81 scsg2 count stop control if the scsgclk output control bit (scsgm3) is cleared to 0, scsgclk is disabled and scsg2 stops counting. scsg2 output (scsgclk) the output signal scsgclk (output to the uart and timer blocks) is controlled by scsgm3. when the scsgclk output control bit (scsgm3) is cleared to 0, scsgclk is disabled.
2-82 7/9/98 timers 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.13 timers this device has five built-in timers: timer x, timer y, timer 1, timer 2, and timer 3. the contents of the timer latch, corresponding to each timer, determine the divide ratio. the timers can be read or written at any time. however, the read and write operations on the high and low-order bytes of the 16-bit timers (timer x and y) must be performed in a specific order. the timers are all down count timers; when the count of a timer reaches 00 16 (0000 16 for timer x and y), an underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to that timer is set to a 1. the divide ratio of a timer is given by 1/( n + 1), where n is the value written to the timer. when the stp instruction is executed or reset is asserted, 01 16 is loaded into timer 2 and the timer 2 reload latch, and ff 16 is loaded into timer 1 and the timer 1 reload latch. figure 2-107. is a block diagram of the five timers. 2.13.1 timer x timer x is a 16-bit timer that has a 16-bit reload latch, and can be placed in one of four modes by setting bits txm4 and txm5 (bits 4 and 5 of the mode register, txm). the bit assignment of the txm is shown in figure 2-104. 2.13.1.1 read and write method read and write operations on the high and low-order bytes of timer x must be performed in a specific order. write method when writing to the timer, the lower order byte is written first. this data is placed in a temporary register that is assigned the same address as timer xl. next, the higher order byte is written. when this is done, the data is placed in the timer xh reload latch and the low-order byte is transferred from its temporary register to the timer xl reload latch. at this point, if the timer x data write control bit (txm0) (bit 0) is 0, the value in the timer x reload latch is also loaded in timer x. if txm0 is 1, the data in the timer x reload latch is loaded in timer x after timer x underflows. address description acronym and value at reset address description acronym and value at reset 0020 16 timer xl txl=ff 0025 16 timer 2 t2=01 0021 16 timer xh txh=ff 0026 16 timer 3 t3=ff 0022 16 timer yl tyl=ff 0027 16 timer x mode register txm=00 0023 16 timer yh tyh=ff 0028 16 timer y mode register tym=00 0024 16 timer 1 t1=ff 0029 16 timer 123 mode register t123m=00 bit5 -txm5 bit4 -txm4 timer x mode 0 0 timer mode 0 1 pulse output mode 1 0 event counter mode 1 1 pulse width measurement mode
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timers 7/9/98 2-83 figure 2-104. txm register read method when reading timer x, the high-order byte is read first. reading the high-order byte causes the values of timer xh and timer xl to be placed in temporary registers assigned the same addresses as timer xh and timer xl. the low-order byte of timer x is then read from its temporary register. this operation assures the correct reading of timer x while it is counting. 2.13.1.2 count stop control if the timer x count stop bit (txm7) (bit 7 of the txm) is set to a 1, timer x stops counting in all four modes. 2.13.1.3 timer mode count source: f / n (where n is 8, 16, 32, or 64) or scsgclk in this mode, each time the timer under?ows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. 2.13.1.4 pulse output mode count source: f / n (where n is 8, 16, 32, or 64) or scsgclk each time the timer x underflows, the output of the cntr0 pin is inverted, and the corresponding timer x interrupt request bit is set to a 1. the repeated inversion of the cntr0 pin output produces a rectangular waveform with a duty ratio of 50 percent. the initial level of the output is determined by the cntr0 polarity select bit (bit 6). when this bit is low, the output starts from a high level. when this bit is high, the output starts from a low level. txm0 timer x data write control bit (bit 0) 0: write data in latch and timer 1: write data in latch only txm2,1 timer x frequency division ratio bits (bits 2,1) bit 2 bit 1 00: f divided by 8 01: f divided by 16 10: f divided by 32 11: f divided by 64 txm3 timer x internal clock select (bit 3) 0: f /n 1: scsgclk (from chip special count source generator) txm5,4 timer x mode bits (bits 5,4) bit 5 bit 4 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode txm6 cntr0 polarity select bit (bit 6) 0: for event counter mode, clocked by rising edge for pulse output mode, start from high level output for cntr0 interrupt request, falling edge active for pulse width measurement mode, measure high period 1: for event counter mode, clocked on falling edge for pulse output mode, start from low level output for cntr0 interrupt request, rising edge active for pulse width measurement mode, measure low period txm7 timer x stop bit (bit 7) 0: count start 1: count stop msb 7 lsb 0 txm7 txm6 txm5 txm4 txm3 txm2 txm1 txm0 access: r/w reset: 00 16 address: 0027 16
2-84 7/9/98 timers 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.13.1.5 event counter mode count source: cntr0 timer countdown is triggered by inputs to the cntr0 pin. each time a timer underflows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. the edge used to clock timer x is determined by the cntr0 polarity select bit (bit 6). 2.13.1.6 pulse width measurement mode count source: f / n (where n is 8, 16, 32, or 64) or scsgclk this mode measures either the high or low-pulse width of the signal on the cntr0 pin. the pulse width measured is determined by the cntr0 polarity select bit (bit 6). when this bit is 0, the high pulse is measured. when this bit is 1, the low pulse is measured. the timer counts down while the level on the cntr0 pin is the polarity selected by the cntr0 polarity select bit. when the timer underflows, the timer x interrupt request bit is set to a 1, the contents of the timer reload latch are reloaded into the timer, and the timer continues counting down. each time the signal polarity switches to the inactive state, a cntr0 interrupt occurs indicating that the pulse width has been measured. the width of the measured pulse can be found by reading timer x during the cntr0 interrupt service routine. 2.13.2 timer y timer y is a 16-bit timer that has a 16-bit reload latch, and can be placed in any of four modes by setting tym4 and tym5 (bits 4 and 5) (see figure 2-105.). the desired mode is selected by modifying the values of tym4 and tym5. bit5 - tym5 bit4 -tym4 timer y mode 0 0 timer mode 0 1 pulse period measurement mode 1 0 event counter mode 1 1 hl pulse width measurement mode
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timers 7/9/98 2-85 figure 2-105. tym register 2.13.2.1 read and write method read and write operations on the high and low-order bytes of timer y must be performed in a speci?c order. write method when writing to the timer, the lower order byte is written first. this data is placed in a temporary register that is assigned the same address as timer yl. next, the high-order byte is written. then, the data is placed in the timer yh reload latch and the low-order byte is transferred from its temporary register to the timer yl reload latch. at this point, if the timer y data write control bit (tym0) (bit 0) is low, the value in the timer y reload latch is also loaded in timer y. if tym0 is 1, the data in the timer y reload latch is loaded in timer y after timer y underflows. read method when reading timer y, the high-order byte is read first. reading the high-order byte causes the values of timer yh and timer yl to be placed in temporary registers that are assigned the same addresses as timer yh and timer yl. the low-order byte of timer y is then read from its temporary register. this operation assures the correct reading of timer y while it is counting. 2.13.2.2 count stop control if the timer y count stop bit (tym7) (bit 7) is set to a 1, timer y stops counting in all four modes. 2.13.2.3 timer mode count source: f / n (where n is 8, 16, 32, or 64) in this mode, each time the timer under?ows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. in timer mode, the signal tyout can also be brought out on the cntr1 pin. this is controlled by tym1 (bit1). msb 7 lsb 0 tym7 tym6 tym5 tym4 tym3 tym2 tym1 tym0 tym0 timer y data write control bit (bit 0) 0: write data in latch and timer 1: write data in latch only tym1 timer y output control bit (bit 1) 0: tyout output disable 1: tyout output enable tym3,2 timer y frequency division ratio bits (bit 3,2) bit 2 bit 1 00: f divided by 8 01: f divided by 16 10: f divided by 32 11: f divided by 64 tym5,4 timer y mode bits (bits 5,4) bit 2 bit 1 0 0: timer mode 0 1: pulse period measurement mode 1 0: event counter mode 1 1: hl pulse width measurement mode (continuously measures high period and low period) tym6 cntr1 polarity select bit (bit 6) 0: for event counter mode, clocked by rising edge for pulse period measurement mode, falling edge detection for cntr1 interrupt request, falling edge active for tyout, start on high output 1: for event counter mode, clocked on falling edge for pulse period measurement mode, rising edge detection for cntr1 interrupt request, rising edge active for tyout, start on low output tym7 timer y stop bit (bit 7) 0: count start 1: count stop access: r/w reset: 00 16 address: 0028 16
2-86 7/9/98 timers 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers each time the timer y underflows, the output of the cntr1 pin is inverted, and the corresponding timer y interrupt request bit is set to a 1. the repeated inversion of the cntr1 pin output produces a rectangular waveform with a duty ratio of 50 percent. the initial level of the output is determined by the cntr1 polarity select bit (bit 6). when this bit is low, the output starts from a high level. when this bit is high, the output starts from a low level. 2.13.2.4 pulse period measurement mode count source: f / n (where n is 8, 16, 32, or 64). this mode measures the period of the event waveform input to the cntr1 pin. cntr1 polarity select bit (tym6) = 0 when the falling edge of an event waveform is detected on the cntr1 pin, the contents of timer y are stored in the temporary register that is assigned the same address as timer y. simultaneously, the value in the timer y reload latch is transferred to timer y, and timer y continues counting down. the falling edge of an event waveform also causes the cntr1 interrupt request; therefore, the period of the event waveform from falling edge to falling edge is found by reading timer y in the cntr1 interrupt routine. the data read from timer y is the data previously stored in its temporary register. cntr1 polarity select bit (tym6) = 1 when the rising edge of an event waveform is detected on the cntr1 pin, the contents of timer y are stored in the temporary register that is assigned the same address as timer y. simultaneously, the value in the timer y reload latch is transferred to timer y, and timer y continues counting down. the rising edge of an event waveform also causes the cntr1 interrupt request; therefore, the period of the event waveform from rising edge to rising edge is found by reading timer y in the cntr1 interrupt routine. the data read from timer y is the data previously stored in its temporary register. each time the timer underflows, the timer y interrupt request bit is set to a 1, the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. 2.13.2.5 event counter mode count source: cntr1 timer countdown is triggered by input to the cntr1 pin. each time a timer underflows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. the edge used to clock timer y is determined by the cntr1 polarity select bit (bit 6). when these bits are 0s, the timers are clocked on the rising edge. when these bits are 1s, the timers are clocked on the falling edge 2.13.2.6 hl pulse-width measurement mode count source: f / n (where n is 8, 16, 32, or 64). this mode continuously measures both the logical high pulse width and the logical low pulse width of an event waveform input to the cntr1 pin. when the falling (or rising) edge of the event waveform is detected on the cntr1 pin, the contents of timer y are stored in the temporary register that is assigned the same address as timer y, regardless of the setting of the cntr1 polarity select bit. simultaneously, the value in the timer y reload latch is transferred to timer y, which continues counting down. the falling or rising edge of an event waveform causes the cntr1 interrupt request; therefore, the width of the event waveform from the falling or rising edge to rising or falling edge is found by reading timer y in the cntr1 interrupt routine. the data read from timer y is the data previously stored in its temporary register.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timers 7/9/98 2-87 each time the timer underflows, the timer y interrupt request bit is set to a 1, the contents of the timer reload latch are loaded into the timer, and the countdown sequence begins again. 2.13.3 timer 1 figure 2-106. t123m register timer 1 is an 8-bit timer with an 8-bit reload latch and has a pulse output option. t123m7 of timer123 mode register (t123m) is the timer 1 and 2 data write control bit. if t123m7 is 1, data written to timer 1 is placed only in the timer 1 reload latch. the latch value is loaded into timer 1 after timer 1 underflows. if t123m7 is 0, the value written to timer 1 is placed in timer 1 and the timer 1 reload latch. at reset, t123m7 is set to a 0. the output signal tout is controlled by t123m5 and t123m6. t123m5 controls the polarity of tout. setting the bit t123m5 to 1 causes tout to start at a low level, and clearing this bit to 0 causes tout to start at a high level. setting t123m6 to 1 enables tout, and clearing t123m6 to 0 disables tout. 2.13.3.1 timer mode count source: f /8 or xcin/2 in timer mode, each time the timer under?ows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. 2.13.3.2 pulse output mode count source: f /8 or xcin/2 timer 1 pulse output mode is enabled by setting t123m6 to 1 and t123m0 to a 0. each time the timer 1 underflows, the output of the tout pin is inverted, and the corresponding timer 1 interrupt request bit is set to a 1. the repeated inversion of the tout pin output produces a rectangular waveform with a duty ratio of 50 percent. the initial level of the output is determined by the tout polarity select bit (t123m5). when this bit is 0, the output starts from a high level. when this bit is 1, the output starts from a low level. t123m0 tout source selection bit (bit 0) 0: tout = timer 1 output 1: tout = timer 2 output t123m1 timer 1 stop bit (bit 1) 0: timer running 1: timer stopped t123m2 timer 1 count source select bit (bit 2) 0: f divided by 8 1: xcin divided by 2 t123m3 timer 2 count source select bit (bit 3) 0: timer 1 under?ow signal 1: f t123m4 timer 3 count source select bit (bit 4) 0: timer 1 under?ow signal 1: f divided by 8 t123m5 tout output active edge selection bit (bit 5) 0: start on high output 1: start on low output t123m6 tout output control bit (bit 6) 0: tout output disabled 1: tout output enabled t123m7 timer 1 and 2 data write control bit (bit 7) 0: write data in latch and timer 1: write data in latch only msb 7 lsb 0 t123m7 t123m6 t123m5 t123m4 t123m3 t123m1 t123m0 access: r/w reset: 00 16 t123m2 address: 0029 16
2-88 7/9/98 timers 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.13.4 timer 2 timer 2 is an 8-bit timer with an 8-bit reload latch. t123m7 (bit 7 of t123m) is the timer 1 and 2 data write control bit. if t123m7 is 1, data written to timer 2 is placed only in the timer 2 reload latch (see figure 2-50). the latch value is loaded into timer 2 after timer 2 underflows. if the t123m7 is 0, the value written to timer 2 is placed in timer 2 and the timer 2 reload latch. at reset, t123m2 is set to a 0. the timer 2 reload latch value is not affected by a change of the count source. however, because changing the count source may cause an inadvertent countdown of the timer, the timer should be rewritten when the count source is changed. 2.13.4.1 timer mode count source: if t123m3 is 0, the timer 2 count source is the timer 1 underflow output. if t123m3 is 1, the timer 2 count source is f . in timer mode, each time the timer under?ows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. 2.13.4.2 pulse output mode count source: if t123m3 is 0, the timer 2 count source is the timer 1 underflow output. if t123m3 is 1, the timer 2 count source is f . timer 2 pulse output mode is enabled by setting t123m6 to a 1 and t123m0 to a 1. each time the timer 2 underflows, the output of the tout pin is inverted, and the corresponding timer 2 interrupt request bit is set to a 1. the repeated inversion of the tout pin output produces a rectangular waveform with a duty ratio of 50 percent. the initial level of the output is determined by the tout polarity select bit (t123m5). when this bit is 0, the output starts from a high level. when this bit is 1, the output starts from a low level. 2.13.5 timer 3 timer 3 is an 8-bit timer with an 8-bit reload latch. the timer 3 reload latch value is not affected by a change of the count source. because changing the count source may cause an inadvertent countdown of the timer, the timer should be rewritten whenever the count source is changed. 2.13.5.1 timer mode count source: if t123m4 is 0, the timer 3 count source is the timer 1 underflow output. if t123m4 is 1, the count source is f /8 in timer mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a 1, the contents of the timer latch are loaded into the timer, and the count down sequence begins again. data written to timer 3 is always placed in timer 3 and the timer 3 reload latch.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timers 7/9/98 2-89 figure 2-107. block diagram of timers x, y, 1, 2, and 3 timer x divider (1/ n ) timer y divider (1/ n ) n =8, 16, 32, 64 scsgclk txm2,1 tym3,2 f 1/8 timer xl latch(8) timer xl (8) timer xh latch(8) timer xh (8) txm0 timer x interrupt request cntr0 interrupt request 10 00 01 txm7 txm5,4 11 txm6 txm3 1 0 1 txm6 txm5, 4 = 01 0 1 q q t txm5,4= 01 rising edge detector tym5,4= 11 tym5,4= 01 or 11 timer yl latch(8) timer yl (8) timer yh latch(8) timer yh (8) tym0 tym7 tym5,4 00 01 11 10 0 tym6 tym= 1 & tym5, 4 = 00 1 tym6 0 1 q q t tym1= 11 and tym5,4 = 0 00 01 10 s tym5,4 11 timer y interrupt request cntr1 interrupt request 0 1 t123m5 t123m6= 1 t123m6= 1 timer 2 latch(8) timer 2 (8) t123m7 timer 2 timer 3 latch(8) timer3 (8) timer 3 1 timer 1 latch(8) timer 1 (8) t123m7 t123m3 t123m4 1 0 0 q q t s tout cntr1 cntr0 falling edge detector interrupt request interrupt request xc in /2 t123m2 0 1 0 t123m1 timer 1 interrupt request 0 1 t123m6 =1 q q t s t123m5 1 0 t123m0 f
2-90 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.14 uart this chip contains two identical uarts. each uart has the following main features: ? clock selection: f or scsgclk ? prescaler selection: x1/x8/x32/x256 divisions (both f and scsgclk) ? baud rate: 11.4 bits/second - 750 kbytes/second (at f = 12mhz) ? error detection: parity/framing/overrun/error sum ? parity: odd/even/none ? stop bits: 1 or 2 ? character length: 7, 8, or 9 bits ? transmit/receive buffer: 2 stages (double buffering) ? handshaking: clear-to-send (cts) and request-to-send (rts) ? interrupt generation conditions: transmit buffer empty or transmit complete, receive buffer full and receive error sum. ? address mode for multi-receiver environment the following descriptions apply to both uarts. the uart receives parallel data from the core or dmac, converts it into serial data, and transmits the results to the send data output terminal utxdx. the uart receives serial data from an external source through the receive data input urxdx, converts it into parallel data, and makes it available to the core or dmac. the uart can detect parity, overrun, and framing errors in the input stream and report the appropriate status information. a double buffering configuration is used for the uarts transmit and receive operations. this double buffering is accomplished by the use of a transmit buffer and transmit shift register on the transmit side and the receive buffer and receive shift register on the receive side. address uart1 description acronym and value at reset address uart2 description acronym and value at reset 0030 16 uart1 mode register u1mod=00 0038 16 uart2 mode register u2mod=00 0031 16 uart1 baud rate generator u1brg=xx 0039 16 uart2 baud rate generator u2brg=xx 0032 16 uart1 status register u1sts=03 003a 16 uart2 status register u2sts=03 0033 16 uart1 control register u1con=00 003b 16 uart2 control register u2con=00 0034 16 uart1 transmit/receiver buffer 1 u1trb1=xx 003c 16 uart2 transmit/receiver buffer 1 u2trb1=xx 0035 16 uart1 transmit/receiver buffer 2 u1trb2=xx 003d 16 uart2 transmit/receiver buffer 2 u2trb2=xx 0036 16 uart1 rts control register u1rtsc=00 003e 16 uart2 rts control register u2rtsc=00 pin description pin description utxd1 uart1 transmit pin is multiplexed with p8 4 utxd2 uart2 transmit pin is multiplexed with p8 0 urxd1 uart1 receive pin is multiplexed with p8 5 urxd2 uart2 receive pin is multiplexed with p8 1 cts1 uart1 cts1 pin is multiplexed with p8 6 cts2 uart2 cts2 pin is multiplexed with p8 2 r ts1 uart1 rts1 pin is multiplexed with p8 7 r ts2 uart2 rts2 pin is multiplexed with p8 3
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification uart 7/9/98 2-91 the uart generates the transmit interrupt when either the transmit buffer empty flag (tbe) or the transmit complete flag (tcm) are set, depending on the state of the transmit interrupt source selection bit (tis, bit 4 of uxcon). the uart generates the receive buffer full interrupt when receiving and the receive buffer full flag is set to a 1. the receive error sum interrupt is generated instead of a receive buffer full interrupt if the uart detects an error when receiving. enabling a transmit or receive operation by setting the ten or the ren (bits 0 and 1 of uxcon) automatically forces the corresponding uart port pins in the appropriate direction. the uart supports an address mode for use in a multi-receiver environment where an address is sent before each message to designate which uart or uarts are to wake-up and receive the message. figure 2-108 is a block diagram of the uart. it is valid for both uart1 and uart2. figure 2-108. uart block diagram 2.14.1 baud rate selection uart rate selection is controlled by the uxbrg and is calculated as follows: baud rate = f / [16 x ( n + 1)] where n denotes the decimal value set in the uxbrg, and where f denotes the clock frequency that depends on the clock selection and the prescale value chosen. either an internal clock f or the output of the chip special count source generator (scsgclk) can be selected as the input clock source by means of the uart clock selection bit (clk, bit 0 of the uart mode register (uxmod)). bits ps0 and ps1 of the uxmod are used to select a prescaling factor for the clock. when the internal clock f is selected, f is the prescaled value of the internal clock f . f = f /1, f /8, f /32, or f /256 uart mode register uart control transmit data bus transmit uart status data bus uxmod register register uxsts uxcon buffer shift register st/stp/pa generator receive buffer register stop and start detect data format bit counter data format bit counter prescaler /1/8/32/256 clock set tx enable tx buffer empty tbe tis = 0 tis = 1 tcm transmit line to utxdx receive line from urxdx receive buffer full interrupt receive error interrupt rx complete rx status errors tx complete le 1,0; pen; stb le 1,0; pen; stb ps 1,0 clksel f scsgclk transmit interrupt baud rate generator rx enable receive shift register to r tsx rts control register from ctsx rts_sel cts_sel data bus
2-92 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers the correspondence between prescale values and baud rate for f = 12mhz is given as an example in table 2-4. when scsgclk is selected, f is the prescaled value of scsgclk. f = scsgclk/1, scsgclk/8, scsgclk/32 or scsgclk/256 example settings for scsgclk, which is controlled by special count source generator registers 1 and 2 (scsg1,2), the prescaler and uxbrg for several common baud rates when f = 12mhz are given in table 2-5. table 2-4. prescale value and baud rate table f = 12mhz f /1 f /8 f /32 f /256 n baud rate n baud rate n baud rate n baud rate 0 750,000.0 1 375,000.0 2 250,000.0 3 187,500.0 4 150,000.0 5 125,000.0 6 107,142.9 7 93,750.0 0 93,750.0 8 83,333.3 1 46,875.0 9 75,000.0 2 31,250.0 10 . 3 23,437.5 0 23,437.5 11 . 4 18,750.0 1 11,718.8 12 . 5 15,625.0 2 7,812.5 13 . 6 13,392.9 3 5,859.4 . .7.4 4,687.5 .. 8 . . 5 3,906.3 . . 6 3,348.2 . . . . 7 2,929.7 0 2,929.7 . . . . 8 2,604.2 1 1,464.8 . . . . . . 2 976.6 . . . . . . 3 732.4 . . . . . . 4 585.9 . . . . . . 5 488.3 . . . . . . 6 418.5 ........ ........ 255 2,929.7 255 366.2 255 91.6 255 11.44
2-93 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.14.2 uart mode register uxmod defines data formats and selects the clock to be used (see figure 2-109). figure 2-109. uxmod register table 2-5. scsgclk, prescaler, and uxbrg settings for common baud rates when f = 12mhz baud rate (hz) scsg (hex) scsg2 (hex) scsgclk rate (hz) prescaler uxbrg (hex) actual baud rate (hz) 50 bypassed 95 80000.00 1/1 63 50.00 75 bypassed 63 120000.00 1/1 63 75.00 110 4e 43 174236.78 1/1 62 110.00 134.5 ac 37 213047.07 1/1 62 134.50 150 bypassed 31 240000.00 1/1 63 150.00 300 bypassed 18 480000.00 1/1 63 300.00 600 18 0b 960000.00 1/1 63 600.00 1200 bypassed 18 480000.00 1/1 18 1200.00 1800 18 13 576000.00 1/1 13 1800.00 2000 bypassed 18 480000.00 1/1 0e 2000.00 2400 18 13 576000.00 1/1 0e 2400.00 3600 18 13 576000.00 1/1 09 3600.00 4800 18 0e 768000.00 1/1 09 4800.00 7200. 18 13 576000.00 1/1 04 7200.00 9600 18 0e 768000.00 1/1 04 9600.00 14400 18 09 1152000.00 1/1 04 14400.00 19200 23 00 11666666.66 1/1 25 19188.60 28800 18 00 11520000.00 1/1 18 28800.00 31250 bypassed bypassed 12000000.00 1/1 17 31250.00 38400 23 00 11666666.66 1/1 12 38377.19 57600 bypassed bypassed 12000000.00 1/1 0c 57692.31 115200 0b 00 11000000.00 1/1 05 114583.33 msb 7 lsb 0 le1 le0 pen pmd stb ps0 clk clk uart clock selection bit (bit 0) 0: f 1: scsgclk ps1,0 internal clock prescaling selection bits (bits 2,1) bit 2 bit 1 0 0: division by 1 0 1: division by 8 1 0: division by 32 1 1: division by 256 stb stop bits selection bit (bit 3) 0: 1 1: 2 pmd parity selection bit (bit 4) 0: even 1: odd pen parity enable bit (bit 5) 0: off 1: on le1,0 uart character length selection bits (bits 7,6) bit 7 bit 6 0 0: 7 bits/character 0 1: 8 bits/character 1 0: 9 bits/character 1 1: reserved access: r/w reset: 00 16 ps1 address: 0030 16 , 0038 16
2-94 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.14.3 uart control register the uxcon specifies the initialization and enabling of a transmit/receive process (see figure 2-110). data can be read from and written to the control register. figure 2-110. uxcon register 2.14.4 uart baud rate register in the uart baud rate register (uxbrg), any value can be specified to obtain the desired baud rate. this register remains in effect whether the uart state is send-enabled, receive-enabled, transmit- in-progress, or receive-in-progress. the contents of this register can be modified only when the uart is not in any of these four states. 2.14.5 uart status register the uart status register (uxsts) reflects both the transmit and receive status (see figure 2-111). the status register is read only. the msb is always 0 during a read operation. writing to this register has no effect. status flags are set and reset under the conditions indicated below. the setting and resetting of the transmit and receive status are not affected by transmit and receive enable flags. the setting and resetting of the receive error flags and receive buffer full flag differs when uart address mode is enabled. these differences are described in section 2.14.9 uart address mode. receive error sum flag the receive error sum flag (ser) is set when an overrun, framing, or parity error occurs after completion of a receive operation. it is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by setting the receive initialization bit (rin). if the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. msb 7 lsb 0 ame tis rin ren ten ten transmission enable bit (bit 0) 0: disable the transmit process 1: enables the transmit process. if the transmit process is disabled (ten cleared) during transmission, the transmit will not stop until completed. ren receive enable bit (bit 1) 0: disable the receive process 1: enables the receive process. if the receive process is disabled (ren cleared) during reception, the receive will not stop until completed. tin transmission initialization bit (bit 2) 0: no action. 1: resets the uart transmit status register bits as well as stopping the transmission operation. the ten bit must be set and the transmit buffer reloaded in order to transmit again. the tin is automatically reset one cycle after tin is set. rin receive initialization bit (bit 3) 0: no action. 1: clears the uart receive status ?ags and the ren bit. if rin is set during receive in progress, receive operation is aborted. the rin bit is automatically reset one cycle after rin is set. tis transmit interrupt source selection bit (bit 4) 0: transmit interrupt occurs when the transmit buffer empty ?ag is set. 1: transmit interrupt occurs when the transmit complete ?ag is set. cts_sel clear-to-send ( cts) enable bit (bit 5) 0: cts function is disabled, p8 6 (or p8 2 ) is used as gpio pin. 1: cts function is enabled, p8 6 (or p8 2 ) is used as cts input. rts_sel request-to-send ( r ts) enable bit (bit 6) 0: rts function is disabled, p8 7 (or p8 3 ) is used as gpio pin. 1: rts function is enabled, p8 7 (or p8 3 ) is used as r ts output. ame uart address mode enable bit (bit 7) 0: address mode disabled. 1: address mode enabled. access: r/w reset: 00 16 rts_sel cts_sel tin address: 0033 16 ,003b 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification uart 7/9/98 2-95 receive overrun flag the receive overrun flag (oer) is set if the previous data in the low-order byte of the receive buffer (uxtrb1) is not read before the current receive operation is completed. it is also set if a receive error occurred for the previous data and the status register is not read before the current receive operation is completed. this flag is reset when the status register is read. this flag is also reset when the hardware reset is asserted or the receiver is initialized by rin. if the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. receive framing error flag the receive framing error flag (fer) is set when the stop bit of the received data is 0. if the stop bit selection bit (stb, bit 3 of uxmod) is set, the flag is set if either of the two stop bits is a 0. this flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by rin. if the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. receive parity error flag the receive parity error flag (per) is set when the parity of received data and the parity selection bit (pmd, bit 4 of uxmod) are different. it is enabled only if the parity enable bit (pen, bit 5 of uxmod) is set. this flag is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by rin. if the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. receive buffer full flag the receive buffer full flag (rbf) is set when the last stop bit of the data is received. it is not set when a receive error occurs. this flag is reset when the low-order byte of the receive buffer (uxtrb1) is read, the hardware reset is asserted, or the receive process is initialized by rin. if the receive operation completes while the status register is being read, the status information is updated upon completion of the status register read. transmission complete flag in the case where no data is contained in the transmit buffer, the transmission complete flag (tcm) is set when the last bit in the transmit shift register is transmitted. in the case where the transmit buffer does contain data, the tcm flag is set when the last bit in the transmit shift register is transmitted if tbe is a 0 or cts handshaking is enabled and ctsx is 1. the tcm flag is also set when the hardware reset is asserted or when the transmitter is initialized by setting the transmit initialization bit (tin, bit 2 of uxcon). it is reset when a transmission operation begins. transmission buffer empty flag the transmission buffer empty flag (tbe) is set when the contents of the transmit buffer are loaded into the transmit shift register. the tbe flag is also set when the hardware reset is asserted or when the transmitter is initialized by tin. it is reset when a write operation is performed to the low-order byte of the transmit buffer (uxtrb1).
2-96 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-111. uxsts register 2.14.6 transmit/receive format transmit method (see figure 2-112.) setup ? de?ne the baud rate by writing a value from 0-255 into the uxbrg. ? set the transmission initialization bit (tin, bit 2 of uxcon), to 1. this will reset the transmit status to a value of 03 16. ? select the interrupt source to be either tbe or tcm by clearing or setting the transmit interrupt source selection bit (tis, bit 4 of uxcon). ? con?gure the data format and clock selection by writing the appropriate value to uxmod. ? set the clear-to-send enable bit (cts_sel, bit 5 of uxcon), if cts handshaking will be used. ? set the transmit enable bit (ten, bit 0 of uxcon), to 1. operation ? when data is written to the low-order byte of the transmit buffer (uxtrb1), tbe is cleared to 0. if 9-bit character length has been selected, the high-order byte of the transmit buffer (uxtrb2) should be written before the low-order byte (uxtrb1). ? if no data is being shifted out of the transmit shift register and cts handshaking is disabled, the data written to the transmit buffer is transferred to the transmit shift register and the tcm ?ag in uxsts is cleared to a 0. in addition, the tbe ?ag is set to a 1, signalling that the next byte of data can be written to the transmit buffer. if cts handshaking is enabled, the operation described above does not take place until ctsx is brought low. ? data from the transmit shift register is transmitted one bit at a time beginning with the start bit and ending with the stop bit. note that the lsb is transmitted ?rst. ? if the ten bit is cleared to a 0 while data is still being transmitted, the transmitter will con- tinue until the last bit is sent. this is also the case when cts handshaking is enabled and ctsx is brought back high during transmission. msb 7 lsb 0 ser oer fer per tbe tcm tcm transmit-complete (transmission register empty) flag (bit 0) 0: data in the transmission register. 1: no data in the transmission register. tbe tx buffer empty flag (bit 1) 0: data in the tx buffer. 1: no data in the tx buffer. rbf rx buffer full flag (bit 2) 0: no data in the rx buffer. 1: data in the rx buffer. per receive parity error flag (bit 3) 0: no receive parity error. 1: receive parity error. fer receive framing error flag (bit 4) 0: no receive framing error. 1: receive framing error. oer receive overrun flag (bit 5) 0: no receive overrun. 1: receive overrun. ser receive error sum flag (bit 6) 0: no receive error. 1: receive error. bit 7 reserved (read 0) access: r only reset: 03 16 rbf address: 0032 16 , 003a 16 reserved
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification uart 7/9/98 2-97 ? when the last bit is transmitted, the tcm ?ag is set to a 1 if the transmit buffer is empty, ten is a 0, or cts handshaking is enabled and ctsx is 1. if the transmit buffer is not empty, ten is a 1, and cts handshaking is disabled or cts handshaking is enabled and ctsx is low, the tcm ?ag is not set because transfer of the contents of the transmit buffer to the transmit shift register occurs immediately. figure 2-112. uart transmit operation waveforms receive method (see figure 2-113.) set up ? de?ne the baud rate by writing a value from 0-255 into uxbrg. ? set the receive initialization bit (rin, bit 3 in the uxcon), to 1. ? con?gure the data format and the clock selection by writing the appropriate value to uxmod. ? set the request-to-send enable bit (rts_sel, bit 6 of uxcon), if rts handshaking will be used. ? set the receive enable bit (ren, bit 1 in the uxcon), to 1. operation ? when a falling edge is detected on the urxdx pin, the value on the pin is sampled at the basic clock rate, which is 16 times faster than the baud rate. if the pin is low for at least two cycles of the basic clock, the start bit is detected. sampling is again performed three times in the approximate middle of the start bit. if two or more of the samples are low, the start bit is deemed valid. if two or more of the samples are not low, the start bit is invalidated and the uart again begins waiting for a falling edge on the urxdx pin. ? once a valid start bit has been detected, input data received through the urxdx pin is read one bit at a time, lsb ?rst, into the receive shift register. as is the case with the start bit, three samples are taken in the approximate middle of each data bit, the parity bit, and the stop bit(s). if two or more of the samples are low, a 0 is latched, and if two or more of the samples are high, a 1 is latched. ? when the number of bits speci?ed by the data format has been received and the last stop bit is uxtrb1 uxbrg utxdx tbe start bit d0 stop bit start bit stop bit clock write tcm
2-98 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers detected, the contents of the receive shift register are transferred to the receive buffer and the receive buffer full flag in the uxsts is set to a 1, if a receive error has not occurred. the rbf interrupt request is also generated at this time if a receive error has not occurred. however, if a receive error did occur, the appropriate error ?ags are set and the receive error sum (ser) interrupt request is generated at this time. ? when the low-order byte of the receive buffer (uxtrb1) is read, the receive buffer full flag is cleared, and the receive buffer is now ready for the next byte. if 9-bit character length has been selected, the high-order byte of the receive buffer (uxtrb2) should be read before reading the low-order byte (uxtrb1). figure 2-113. uart receive operation waveforms 2.14.7 interrupts the transmit and receive interrupts are generated under the conditions described below. the generation of the receive interrupts differs when uart address mode is enabled. the differences are described in section 2.14.9 uart address mode. transmit interrupts the uart generates a transmit interrupt to the cpu core. the source of the transmit interrupt is selectable by setting tis. ? if tis = 0, the transmit interrupt is generated when the transmit buffer register becomes empty (that is, when tbe ?ag set). ? if tis = 1, the transmit interrupt is generated after the last bit is sent out of the transmit shift register and no data has been written to the transmit buffer or cts handshaking is enabled and ctsx is high (that is, when tcm ?ag set). receive interrupts the uart generates the receive buffer full (rbf) and receive error sum (ser) interrupts to the cpu core when receiving. ? the rbf interrupt is generated when a receive operation completes and a receive error is not generated. ? the ser interrupt is generated when an overrun, framing or parity error occurs. uxbrg urxdx rbf start bit d0 stop bit start bit clock d0 edge detection 2-of-3 sampling 2-of-3 sampling 2-of-3 sampling 2-of-3 sampling 2-of-3 sampling edge detection uxtrb1 read
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification uart 7/9/98 2-99 2.14.8 clear-to send ( ctsx) and request-to-send ( r tsx) signals the uart, as a transmitter, can be configured to recognize the clear-to-send ( ctsx) input as a handshaking signal. as a receiver, the uart can be configured to generate the request-to-send ( rtsx) handshaking signal. clear-to-send ( ctsx ) input cts handshaking is enabled by setting the clear-to-send enable bit (cts_sel, bit 5 of uxcon) to a 1. if cts handshaking is enabled, when ten is a 1 and the low-order byte of the transmit buffer (uxtrb1) is loaded, the uart begins the transmission process when the ctsx pin is asserted (low input). after beginning a send operation, the uart does not stop sending until the transmission is completed, even if ctsx is deasserted (high input). if ten is cleared to 0, the uart will not stop transmitting and the port pins will remain under the control of the uart until the end of the transmission. if cts handshaking is disabled and ten is a 1, the uart begins the transmission process as soon as data is available in the low-order byte of the transmit buffer (uxtrb1). figure 2- 115 shows a timing example for ctsx. request-to-send ( rtsx ) output rts handshaking is enabled by setting the request-to-send enable bit (rts_sel, bit 6 of uxcon) to a 1. when rts handshaking is enabled, the uart drives the rtsx output low or high based on the following conditions: assertion conditions (driven low): ? the receive enable bit (ren) is set to a 1. ? receive operation has completed with the reception of the last stop bit, ren is still a 1, and the programmable assertion delay has expired. de-assertion conditions (driven high): ? a valid start bit is detected and ren is a 1. ? ren is cleared to a 0 before a receive operation is in progress. ? receive operation has completed and ren is a 0. ? uart receiver is initialized (rin is set to a 1). the delay time from the reception of the last stop bit to the re-assertion of rtsx is programmable. the amount of delay is selected by setting the rts assertion delay count bits (rts3~0, bits 3 to 0 of uxrtsc) (see figure 2-114). the time can be from no delay to 120 bit-times, with the delay beginning from the middle of the last stop bit. if a start bit is detected before the assertion delay has expired, the delay countdown is stopped and the rtsx pin remains high. a full assertion delay countdown will begin again once the last stop bit of the incoming data has been received. figure 2-115 shows a timing example for rtsx.
2-100 7/9/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-114. uxrtsc register figure 2-115. ctsx and rtsx timing examples 2.14.9 uart address mode the uart address mode is intended for use in a multi-receiver environment where an address is sent before each message to designate which uart or uarts are to wake-up and receive the message. an address is identified by the msb of the incoming data byte being a 1. the bit is 0 for non-address data. uart address mode can be used in either 8-bit or 9-bit character length mode. the character length is chosen by writing the appropriate values to the uart character length selection bits (le1,0). uart address mode is enabled by setting the uart address mode enable bit (ame) to 1. when uart address mode is enabled, the msb of a newly received byte of data (that is either 8 or 9 bits in length) is examined if a valid stop bit is detected and a parity error has not occurred (if parity is enabled). if the msb is 1, then the receive buffer full interrupt and flag are set and ame is automatically cleared, disabling uart address mode. if the msb is 0, then the receive buffer full interrupt is not set. however, the rbf flag is still set for this case. if a valid stop bit is not detected msb 7 lsb 0 rts2 rts1 rts0 bits 0-3 reserved (read/write 0) rts3:0 rts assertion delay count 3:0 (bits 7,6,5,4) 0000: no delay, r ts asserts immediately after receive operation completes. 0001: r ts asserts 8 bit-times after receive operation completes. 0010: r ts asserts 16 bit-times after receive operation completes. 0011: r ts asserts 24 bit-times after receive operation completes. . . . 1000: r ts asserts 64 bit-times after receive operation completes. . . . 1110: r ts asserts 112 bit-times after receive operation completes. 1111: r ts asserts 120 bit-times after receive operation completes. access: r/w reset: 80 16 rts3 address: 0036 16 , 003e 16 reserved reserved reserved reserved programmable delay cts (input) txd (output) rxd (input) rts (output) data stop start data start data in both examples, the transmit and receive have already been enabled
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification uart 7/9/98 2-101 or a parity error has occurred, neither the receive buffer full flag nor interrupt is set and the msb of the data is not examined. instead, either the framing error or parity error flag is set, the error sum flag is set, and the error sum interrupt is set. while in uart address mode, the generation of overrun errors is disabled after the first byte of data is received. therefore, when non-address data is received without errors while in the uart address mode, it is not necessary to read the uart receive buffer prior to the reception of the next byte of data. also, if a framing or parity error occurs while in uart address mode, it is not necessary to read the uxsts prior to the reception of the next byte of data. however, an overrun error will occur if an address byte is received and the uart receive buffer is not read before a new byte of data is received. this is the case because the uart address mode was automatically disabled when the address byte was received. also, an overrun error will occur for the first byte received after uart address mode is enabled if the preceding byte received did not generate an error and the uart receive buffer was not read, or the preceding byte did generate an error and uxsts was not read. when the msb is 1 and the uart address mode is automatically disabled, the uart reverts back to normal reception mode. in normal reception mode, the value of the msb of each byte of received data has no effect on the setting of the receive buffer full interrupt or the determination of overrun errors.
2-102 7/9/98 serial i/o 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.15 serial i/o the serial i/o has the following main features: ? synchronous transmission or reception ? handshaking via srd y output signal ? 8-bit character length ? interrupt after transmission or reception ? internal clock (when serial i/o synchronous clock select bit is 1, internal clock source divided by 2, 4, 8, 16, 32, 64, 128, 256 can be selected). if bit 1 of sio control register2 is 0, internal clock source = f ; if bit 1 of sio control register2 is 1, internal clock source = scsgclk.) ? external clock (when sio synchronous clock select bit is 1, an external clock input from the sclk pin is selected). a block diagram of the clock synchronous sio is shown in figure 2-116. 2.15.1 sio control register the serial i/o control register controls the various sio functions (see figure 2-117.). all of this register's bits can be read from and written to by software. at reset, this register is cleared to 00 16 . the sio control register determines whether the devices pins are used as ordinary i/o ports or as sio function pins. this register also determines the transfer direction and transfer clock for serial data. 2.15.2 sio operation an internal clock or an external clock can be selected as the synchronous clock. when the internal clock is chosen, dividers are built in to provide eight different clock selections. the start of a transfer is initiated by a write signal to the sio shift register (address 002a 16 ). the srdy signal then drops active low. on the negative edge of the transfer clock srdy returns high and the data is transmitted out the stxd pin. data is latched in from the srxd pin on the rising edge of the transfer clock. if an internal clock is selected, the stxd pin enters a high-impedance state after an 8-bit transfer is completed. if an external clock is selected, the contents of the serial i/o register continue to be shifted while the send/receive clock is being input. therefore, the clock needs to be controlled by the external source. also there is no stxd high-impedance function after data is transferred. address description acronym and value at reset 002a 16 sio shift register siosht=xx 002b 16 sio control register 1 siocon1=00 002c 16 sio control register 2 siocon2=00 name pin srd y is multiplexed with p8 0 sclk is multiplexed with p8 1 srxd is multiplexed with p8 2 stxd is multiplexed with p8 3
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification serial i/o 7/9/98 2-103 regardless of whether an internal or external clock is selected, after an 8-bit transfer, the interrupt request bit is set. figure 2-119 shows the timing for the serial i/o with the lsb-first option selected. the sio can be operated in slave mode. in slave mode the srdy pin becomes an input from a master. if srdy is held high, the shift clock is inhibited, stxd is tri-stated, and shift count is reset. if srdy is held low, then the normal shift operation is performed. figure 2-116. clock synchronous sio block diagram 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f 1 scsel data bus synchronous circuit srd y p80 latch p81 latch sclk p83 latch stxd sio counter sio interrupt request sio shift register srxd 0 1 psel psel 0 1 rdysel external clock 0 scsgclk 1 0 0 1 clksel srd y slave divider
2-104 7/9/98 serial i/o 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 2-117. sio control register 1 figure 2-118. sio control register 2 figure 2-119. normal mode sio function timing (with lsb-first selected) msb 7 lsb 0 scsel tdsel rdysel psel iscsel1 iscsel0 iscsel0-2 internal synchronization clock select bits (bits 2,1,0) bit 2 bit 1 bit 0 0 0 0: internal clock divided by 2. 0 0 1: internal clock divided by 4. 0 1 0: internal clock divided by 8. 0 1 1: internal clock divided by 16. 1 0 0: internal clock divided by 32. 1 0 1: internal clock divided by 64. 1 1 0: internal clock divided by 128. 1 1 1: internal clock divided by 256. psel sio port selection bit (bit 3) 0: i/o port 1: txd output, sclk function rdysel srd y output select bit (bit 4) 0: i/o port 1: srd y signal tdsel transfer direction select bit (bit 5) 0: lsb ?rst 1: msb ?rst scsel synchronization clock select bit (bit 6) 0: external clock 1: internal clock ochcont txd output channel control bit (bit 7) 0: cmos output 1: n-channel open drain output access: r/w reset: 00 16 iscsel2 ochcont address: 002b 16 slave slave mode selection bit (bit 0) 0: normal mode 1: slave mode (to enter slave mode, bit 4 of sio control register 1 also needs to be set) clksel sio internal clock selection bit (bit 1) 0: f 1: scsgclk rxdsel srxd input selection bit (bit 2) 0: srxd input disabled 1: srxd input enabled bits 3-4 reserved (read/write 1) bits 5-7 reserved (read/write 0) msb 7 lsb 0 clksel slave access: r/w reset: rxdsel reserved address: 002c 16 reserved reserved reserved reserved 18 16 synchronous clock transfer clock sio register receive enable sio output sio input write signal signal srd y interrupt request bit set see note note: when the internal clock is selected, the txd pin goes into high- impedance after the data is transferred. d0 d1 d2 d3 d4 d5 d6 d7
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification low power modes 7/9/98 2-105 2.16 low power modes this device has two low-power dissipation modes: ? stop ? wait 2.16.1 stop mode use of the stop mode allows the mcu to be placed in a state where no internal excitation of the circuitry is taking place, thus resulting in extremely low power dissipation. the mcu enters the stop mode when the stp instruction is executed. the internal state of the mcu after execution of the stp instruction is as follows: ? all internal oscillation stops with p2 and p2per held high and p1 and p1per held low. ? timer 1 and timer 2 are loaded with ff 16 and 01 16 respectively. ? the count source for timer 1 is set to f /8 and the count source for timer 2 is set to timer 1 under?ow. figure 2-120. stp cycle timing diagram oscillation is restarted (that is, all clocks other than p1 and p2 begin to oscillate) when a reset or an external interrupt is received. the interrupt control bit of the interrupt used to release the stop mode must be set to a 1 and the i flag set to a 0 prior to the execution of the stp instruction. to allow the oscillation source time to stabilize, the oscillation source is connected as the clock source for the wake-up timer (timer 1 and timer 2 cascaded). when timer 2 underflows, the system clocks p1 and p2 are restarted and the mcu services the interrupt that caused the return from the stop state. it f out p1 p2 sync out rd wr address data opcode invalid s,cpma2 pc + 1 pc x in p1per p2per intreq stpsig cpuosc (pc + 1)h sleep period timer countdown (oscillator stabilization) timer 2 under?ow start of interrupt service routine note: return from a stp instruction is caused by an interrupt, followed by the countdown and under?ow of timer 2
2-106 7/9/98 low power modes 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers then services any other enabled interrupts that occurred, in the order of their respective priorities, and returns to its state prior to the execution of the stp instruction. the timing for the stp instruction is shown in figure 2-120. 2.16.2 wait mode use of the wait mode allows the microcomputer to be placed in a state where excitation of the cpu is stopped, but the clocks to the peripherals continue to oscillate. this mode provides lower power dissipation during the idle periods and quick wake-up time. the microcomputer enters the wait mode when the wit instruction is executed. after the instruction execution, p2 is held high and p1 is held low. returning from wait mode is accomplished just as it is when returning from stop mode, with the exception that you need not provide time for the oscillator to stabilize, because the oscillation never stopped. because p1per and p2per continue to oscillate in the wait mode, any peripheral interrupt can be used to bring the microcomputer out of the wait mode. the timing for the wit instruction is shown in figure 2-121. figure 2-121. wit cycle timing diagram f out p1 p2 sync out rd wr address data opcode invalid s,cpma2 pc + 1 pc x in p1per p2per intreq stpsig (pc + 1)h sleep period start of interrupt service routine note: return from a wit instruction is caused by an interrupt.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification reset 7/9/98 2-107 2.17 reset this device is reset if the reset pin is held low for a minimum of 2 m s while the supply voltage is between 4.75 and 5.25volts. when the reset pin returns high, the reset sequence commences (see figure 2-122). to allow the oscillation source the time to stabilize, a delay is generated by the countdown of timer 1 and timer 2 cascaded with ff 16 loaded in timer 1 and 01 16 loaded in timer 2. after the reset sequence completes, program execution begins at the address whose high-order byte is the contents of address fffa 16 and whose low-order byte is the contents of address fffb 16 . figure 2-122. internal processing sequence after reset f out p1 p2 sync out address data ? reset first timer countdown from 01ff 16 ? ? ? ? fffa fffb ? ? ? ? ? adh adl adl, adh opcode
2-108 7/9/98 key-on wake-up 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 2.18 key-on wake-up this device contains a key-on wake-up interrupt function. the key-on wake-up interrupt function is one way of returning from a power-down state caused by the stp or wit instructions. this interrupt is generated by applying low level to any pin of port 2. if a key matrix is connected as shown in figure 2-123, the microcomputer can be returned to a normal state by pressing any one of the keys. key-on wake-up is enabled in single-chip mode only. figure 2-123. port 2 with key-on wake-up function key-on wake up interrupt request port p2 input read circuit port pxx l level output from arbitrary port xx p2 7 output p2 6 output p2 5 output p2 4 output p2 3 input p2 2 input p2 1 input p2 0 input off chip on chip pull p2 register bit 0 port p20 latch port p2 direction register bit 0 = "0" port p2 direction register bit 1 = "0" port p2 direction register bit 2 = "0" port p2 direction bit 7 = 1 port p2 direction register bit 6 = 1 port p2 direction register bit 5 = 1 port p2 direction register bit 4 = 1 port p2 direction register bit 3 = "0" port p21 latch port p22 latch port p23 latch port p24 latch port p25 latch port p26 latch port p27 latch register pull p2 register bit 1 pull p2 register bit 2 pull p2 register bit 3 pull p2 register bit 4 pull p2 register bit 5 pull p2 register bit 7 pull p2 register bit 6
mitsubishi semiconductor america, inc. preliminary chapter 3 electrical characteristics 3.1 absolute maximum ratings. . . .3-3 3.2 recommended operating conditions . . . . . . . . . . . . . . . . . 3-4 3.3 electrical characteristics . . . . . 3-6 3.4 timing requirements and switching characteristics . . . . 3-8
3-2 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification absolute maximum ratings 6/2/98 3-3 3 electrical characteristics 3.1 absolute maximum ratings note 1. maximum power dissipation is based on package heat dissipation characteristics, not chip power consumption. table 3-1. absolute maximum ratings symbol parameter conditions limits unit v cc power supply -0.3 to 7.0 v av cc analog power supply -0.3 to v cc + 0.3 v v i input voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 values are with respect to v ss . output transistors are in off state. -0.3 to v cc + 0.3 v v i input voltage reset, x in , xc in -0.3 to v cc + 0.3 v v i input voltage cnv ss -0.3 to 13 v v i input voltage usb d+, d- -0.5 to 3.8v v v o output voltage p0, p1, p2, p3, p4, p5, p6, p7, p8, x out , xc out -0.3 to v cc + 0.3 v p d power dissipation note 1 ta = 25 c 750 mw t opr operating temperature -20 to +85 c t stg storage temperature -40 to +125 c
3-4 6/2/98 recommended operating conditions 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 3.2 recommended operating conditions note 1. the peak output current is the peak current ?owing through any pin of the listed ports. note 2. the average output current is an average current value measured over 100ms. note 3. the total peak output current is the peak current ?owing through all pins of the listed ports. table 3-2. recommended operating conditions (v cc = 4.15 to 5.25v, v ss = 0v, ta = -20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. v cc supply voltage 4.15 5 5.25 v av cc analog supply voltage 4.15 5 v cc v v ss supply voltage 0v av ss analog supply voltage 0v v ih h input voltage reset, x in , xc in , cnv ss 0.8v cc v cc v v ih h input voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 0.8v cc v cc v v ih h input voltage p2 (when ptc6 = 0) 0.5v cc v cc v v ih h input voltage p5 7 -p5 4 , p6, p7 2 (when mbi inputs and ptc7 = 1) 2.0 v cc v v il l input voltage reset, x in , xc in , cnv ss 0 0.2v cc v v il l input voltage p0, p1, p2, p3, p4, p5, p6, p7, p8 0 0.2v cc v v il l input voltage p2 (when ptc6 = 0) 0 0.16 v cc v v il l input voltage p5 7 -p5 4 , p6, p7 2 (when mbi inputs and ptc7 = 1) 0 0.8 v i ol (peak) l peak output current note 1 p0, p1, p2, p3, p4, p5, p6, p7, p8 10 ma i ol (avg) l average output current note 2 p0, p1, p2, p3, p4, p5, p6, p7, p8 5ma i oh (peak) h peak output current note 1 p0, p1, p2, p3, p4, p5, p6, p7, p8 -10 ma i oh (avg) h average output current note 2 p0, p1, p2, p3, p4, p5, p6, p7, p8 -5 ma si ol (peak) l total peak output current note 3 p0, p1, p2, p3, p4, p5, p6, p7, p8 80 ma s i ol (avg) l total average output current note 4 p0, p1, p2, p3, p4, p5, p6, p7, p8 40 ma s i oh (peak) h total peak output current note 3 p0, p1, p2, p3, p4, p5, p6, p7, p8 -80 ma s i ol (avg) h total average output current note 4 p0, p1, p2, p3, p4, p5, p6, p7, p8 -40 ma f(cntr0) timerx - input frequency note 5 5 mhz f(cntr1) timery - input frequency note 5 5 mhz f(x in ) clock frequency note 5 24 mhz f(xc in ) clock frequency note 5,6 32.768 50/5.0 khz/mhz
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification recommended operating conditions 6/2/98 3-5 note 4. the total average output current is an average current value measured over 100ms. note 5. the oscillation frequency has a 50% duty cycle. note 6. the maximum oscillation frequency of 50khz is for a crystal oscillator connected between xc in and xc out . an external clock signal having a maximum frequency of 5mhz can be input to xc in .
3-6 6/2/98 electrical characteristics 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 3.3 electrical characteristics table 3-3. electrical characteristics (v cc = 4.15 to 5.25v, v ss = 0v, ta = -20 to 85 c, unless otherwise noted) symbol parameters test conditions limits unit min typ. max v oh h output current p0, p1, p2, p3, p4, p5, p6, p7, p8 ioh = -10ma v cc - 2.0 v v ol l output current p0, p1, p2, p3, p4, p5, p6, p7, p8 iol = 10ma 2.0 v v t + ~v t - hysteresis cntr0, cntr1, int0, int1, key- on wakeup (p2), rdy, hold 0.5 v urxd1, urxd2 (sclk), cts2 (srxd), srd y, cts1 0.5 v reset 0.5 v i ih h input current p0, p1, p2, p3, p4, p5, p6, p7, p8 v i = v cc 5 m a reset, cnv ss 5 m a x in 920 m a xc in 5 m a i il l input current p0, p1, p3, p4, p5, p6, p7, p8 v i = v ss -5 m a p2 v i = v ss (pullups off) -5 m a v cc = 5v, v i = v ss (pullups on) -30 -70 -140 m a reset v i = v ss -5 m a cnv ss -20 x in -9 -20 m a xc in -5 m a v ram ram retention voltage clocks stopped 2.0 v i cc supply current (output transistors are isolated) normal mode f(x in ) = 24mhz, f = 6mhz, usb operating, frequency synthesizer on note 1 55 70 ma f(x in ) = 24mhz, f = 12mhz, usb operating, frequency synthesizer on note 1 70 90 ma f(x in ) = 24mhz, f = 12mhz, usb suspended, frequency synthesizer on, usb clock disabled note 2 35 45 ma wait mode f(x in ) = 24mhz, f = 12mhz, usb suspended, frequency synthesizer on, usb clock disabled note 3 7.5 10 ma f(xc in ) = 32khz, f = 16khz, usb disabled, frequency synthesizer off, transceiver voltage converter off note 4 610 m a stop mode transceiver voltage converter on with usbc3 = 1 (low current mode) 200 250 m a t a = 25 c, transceiver voltage converter off 0.1 1 m a t a = 85 c, transceiver voltage converter off 10 m a
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification electrical characteristics 6/2/98 3-7 note 1. icc test conditions: single chip mode (run state) square wave clock input on x in (x out drive disabled) i/o pins isolated frequency synthesizer running usb operating with transceiver voltage converter enabled cpu and dmac running timers and scsg running both uarts transmitting mbi and sio disabled note 2. icc test conditions same as note 1 except for the following: usb in suspend state with usb clock disabled note 3. icc test conditions: single chip mode (wait state) square wave clock input on x in (x out drive disabled) i/o pins isolated frequency synthesizer running usb in suspend state with usb clock disabled transceiver voltage converter enabled timers and scsg running cpu and dmac not running both uarts, sio, and mbi disabled note 4. icc test conditions: single chip mode (wait state) x in /x out oscillation disabled square wave clock input on xc in (xc out drive disabled) i/o pins isolated frequency synthesizer disabled usb and usb clock disabled transceiver voltage converter disabled timers and scsg running cpu and dmac not running both uarts, sio, and mbi disabled
3-8 6/2/98 timing requirements and switching characteristics 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 3.4 timing requirements and switching characteristics table 3-4. timing requirements and switching characteristics (v cc = 4.15 to 5.25v, v ss = 0v, ta = -20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. inputs t w(reset) reset input low pulse width 2 m s t c(x in ) clock input cycle time 41.66 ns twh(x in ) clock input high pulse width 0.4* t c(x in )ns twl(x in ) clock input low pulse width 0.4* t c(x in )ns tc(xc in ) clock input cycle time 200 ns twh(xc in ) clock input high pulse width 0.4*tc(xc in )ns twl(xc in ) clock input low pulse width 0.4*tc(xc in )ns interrupts tc(int) int0, int1 input cycle time 140 ns twh(int) int0, int1 input high pulse width 55 ns twl(int) int0, int1 input low pulse width 55 ns tc(cntri) cntr0, cntr1 input cycle time 200 ns twh(cntri) cntr0, cntr1 input high pulse width 80 ns twl(cntri) cntr0, cntr1 input low pulse width 80 ns timers td( f -tout) timer tout delay time note 1 15 ns td( f -cntr0) timer cntr0 delay time (pulse output mode) note 1 15 ns tc(cntre0) timer cntr0 input cycle time (event counter mode) 200 ns twh(cntre0) timer cntr0 input high pulse width (event counter mode) 0.4*tc(cntre0) ns twl(cntre0) timer cntr0 input low pulse width (event counter mode) 0.4*tc(cntre0) ns td( f -cntr1) timer cntr1 delay time (pulse output mode) note 1 15 ns tc(cntre1) timer cntr1 input cycle time (event counter mode) 200 ns twh(cntre1) timer cntr1 input high pulse width (event counter mode) 0.4*tc(cntre1) ns twl(cntre1) timer cntr1 input low pulse width (event counter mode) 0.4*tc(cntre1) ns sio tc(sclke) sio external clock input cycle time 400 ns twh(sclke) sio external clock input high pulse width 190 ns twl(sclke) sio external clock input low pulse width 180 ns tsu(srxd-sclke) sio receive setup time (external clock) 15 ns th(sclke-srxd) sio receive hold time (external clock) 10 ns td(sclke-stxd) sio transmit delay time (external clock) 25 ns tv(sclke-srdy) sio srd y valid time (external clock) 26 ns tc(sclki) sio internal clock output cycle time 166.66 ns twh(sclki) sio internal clock output high pulse width 0.5*tc(sclki)-5 ns twl(sclki) sio internal clock output low pulse width 0.5*tc(sclki)-5 ns tsu(srxd-sclki) sio receive setup time (internal clock) 20 ns th(sclki-srxd) sio receive hold time (internal clock) 5 ns td(sclki-stxd) sio transmit delay time (internal clock) 5 ns
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timing requirements and switching characteristics 6/2/98 3-9 note 1. timer clock is f or a derivative of f . mbi (separate r and w type mode) tsu(s-r) s0, s1 setup time for read 0 ns tsu(s-w) s0, s1 setup time for write 0 ns th(r-s) s0, s1 hold time for read 0 ns th(w-s) s0, s1 hold time for write 0 ns tsu(a-r) a0 setup time for read 10 ns tsu(a-w) a0 setup time for write 10 ns th(r-a) a0 hold time for read 0 ns th(w-a) a0 hold time for write 0 ns tw(r) read pulse width 50 ns tw(w) write pulse width 50 ns tsu(d-w) data input setup time before write 25 ns th(w-d) data input hold time after write 0 ns ta(r-d) data output enable time after read 40 ns tv(r-d) data output disable time after read 10 ns tv(r-obf) obf output transmission time after read 40 ns td(w-ibf) ibf output transmission time after write 40 ns mbi (r/ w type mode) tsu(s-e) s0, s1 setup time 0 ns th(e-s) s0, s1 hold time 0 ns tsu(a-e) a0 setup time 10 ns th(e-a) a0 hold time 0 ns tsu(rw-e) r/ w setup time 10 ns th(e-rw) r/ w hold time 10 ns tw(e) enable pulse width 50 ns tw(e-e) enable pulse interval 50 ns tsu(d-e) data input setup time before write 25 ns th(e-d) data input hold time after write 0 ns ta(e-d) data output enable time after read 40 ns tv(e-d) data output disable time after read 10 ns tv(e-obf) obf output transmission time after e inactive 40 ns td(e-ibf) ibf output transmission time after e inactive 40 ns table 3-4. timing requirements and switching characteristics (v cc = 4.15 to 5.25v, v ss = 0v, ta = -20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max.
3-10 6/2/98 timing requirements and switching characteristics 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 3-1. reset, clock, interrupts and timers timing diagram tw(reset) 0.2vcc 0.8vcc reset x in 0.2vcc 0.8vcc twh(x in ) twl(x in ) tc(x in ) xc in 0.2vcc 0.8vcc twh(xc in ) twl(xc in ) tc(xc in ) interrupts cntr0, cntr1 0.2vcc 0.8vcc twh(int),twh(cntri) twl(int),twl(cntri) int0, int1 , tc(int), tc(cntri) timers f tout 0.5vcc td( f -tout) cntr0, cntr1 td( f -cntr0,1) inputs 0.5vcc 0.5vcc cntr0, cntr1 0.2vcc 0.8vcc twh(cntre0,1) twl(cntre0,1) tc(cntre0,1)
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timing requirements and switching characteristics 6/2/98 3-11 figure 3-2. sio timing diagram tc(sclke,i) 0.2vcc 0.8vcc sio 0.8vcc 0.2vcc tsu(srxd-sclke,i) th(sclke,i-srxd) td(sclke,i-stxd) tv(sclke-srdy) 0.8vcc sclk srxd stxd srd y twh(sclke,i) twl(sclke,i) 0.5vcc
3-12 6/2/98 timing requirements and switching characteristics 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 3-3. mbi timing diagram (separate r and w type mode) s0, s1 t su(s-w) t h(w-s) 0.2vcc (0.8v) read write a 0 s0, s1 r dq 0 -dq 7 obf ibf dq 0 -dq 7 a 0 t su(a-r) t h(r-a) t su(s-r) t h(r-s) t w(r) t a(r-d) t v(r-d) t v(r-obf) t su(a-w) t h(w-a) t su(d-w) t h(w-d) t d(w-ibf) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc 0.2vcc (0.8v) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.8vcc 0.2vcc 0.8vcc 0.2vcc 0.8vcc (2.0v) 0.2vcc (0.8v) w t w(w) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc note: ttl input levels in parenthesis (ttl levels selected when ptc7 = 1) 0.8vcc (2.0v) 0.2vcc (0.8v)
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timing requirements and switching characteristics 6/2/98 3-13 figure 3-4. mbi timing diagram (r/ w type mode) a 0 read obf, ibf dq 0 -dq 7 t su(a-e) t h(e-a) t su(s-e) t h(e-s) t a(e-d) t v(e-d) e t w(e-e) t w(e) s0, s1 write dq 0 -dq 7 t h(e-d) t v(e-obf) t d(e-ibf) r/ w t su(e-d) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc (0.8v) 0.2vcc (0.8v) 0.8vcc (2.0v) 0.2vcc (0.8v) 0.8vcc 0.2vcc 0.8vcc (2.0v) 0.2vcc (0.8v) 0.2vcc note: ttl input levels in parenthesis (ttl levels selected when ptc7 = 1)
3-14 6/2/98 timing requirements and switching characteristics 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers note 1. . measurement conditions: iohl = 5ma, c l = 50pf table 3-5. memory expansion mode and microprocessor mode timing (v cc = 4.15 to 5.25v, v ss = 0v, ta = -20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. tc( f ) f clock cycle time 83.33 ns twh( f ) f clock h pulse width 0.5*tc( f )-5 ns twl( f ) f clock l pulse width 0.5*tc( f )-5 ns td( f -ah) address bus ab15-ab8 delay time with respect to f 31 ns tv( f -ah) address bus ab15-ab8 valid time with respect to f 5ns td( f -al) address bus ab7-ab0 delay time with respect to f 33 ns tv( f -al) address bus ab7-ab0 valid time with respect to f 5ns td( f -wr) wr delay time 6 ns tv( f -wr) wr valid time 3 ns td( f -rd) rd delay time 6 ns tv( f -rd) rd valid time 3 ns td( f -sync) sync out delay time 6ns tv( f -sync) sync out valid time 4ns td( f -dma) dma out delay time 25 ns tv( f -dma) dma out valid time 5ns tsu(rdy- f ) rdy setup time with respect to f 21 ns th( f -rdy) rdy hold time with respect to f 0ns tsu(hold- f ) hold setup time 21 ns th( f -hold) hold hold time 0 ns td( f -hlda) hld a delay time 25 ns tv( f -hlda) hld a valid time 25 ns tsu(db- f ) data bus setup time with respect to f 7ns th( f -db) data bus hold time with respect to f 0ns td( f -db) data bus delay time with respect to f 22 ns tv( f -db) data bus valid time with respect to f note 1 13 ns twl(wr) wr pulse width 0.5*tc( f )-5 ns twl(rd) rd pulse width 0.5*tc( f )-5 ns td(ah-wr) wr delay time after stable address ab15-ab8 0.5*tc( f )-28 ns td(al-wr) wr delay time after stable address ab7-ab0 0.5*tc( f )-30 ns tv(wr-ah) address bus ab15-ab8 valid time with respect to wr 0 ns tv(wr-al) address bus ab7-ab0 valid time with respect to wr 0 ns td(ah-rd) rd delay time after stable address ab15-ab8 0.5*tc( f )-28 ns td(al-rd) rd delay time after stable address ab7-ab0 0.5*tc( f )-30 ns tv(rd-ah) address bus ab15-ab8 valid time with respect to rd 0 ns tv(rd-al) address bus ab7-ab0 valid time with respect to rd 0 ns tsu(rdy-wr) rdy setup time with respect to wr 27 ns th(wr-rdy) rdy hold time with respect to wr 0 ns tsu(rdy-rd) rdy setup time with respect to rd 27 ns th(rd-rdy) rdy hold time with respect to rd 0 ns tsu(db-rd) data bus setup time with respect to rd 13 ns th(rd-db) data bus hold time with respect to rd 0 ns td(wr-db) data bus delay time with respect to wr 20 ns tv(wr-db) data bus valid time with respect to wr note 1 10 ns
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timing requirements and switching characteristics 6/2/98 3-15 figure 3-5. microprocessor and memory expansion mode timing diagram 1 f ab15-ab8 ab7-ab0 sync out rd, wr rdy db0-db7 (cpu read phase) db0-db7 (cpu write phase) t c( f ) 0.5vcc td( f - ah) 0.5vcc twh( f ) td( f - al ) th( f - rdy) tsu(rdy - f ) td( f - db) tv( f - db) tsu(db - f ) td( f - rd ) 0.5vcc 0.8vcc 0.2vcc 0.8vcc 0.2vcc 0.5vcc th( f - db) tv( f - rd) tv( f - al) tv( f - ah) twl( f ) 0.5vcc 0.5vcc dma out td( f - sync ) 0.5vcc td( f - dma ) 0.5vcc tv( f - dma) hold th( f - hold) tsu(hold - f ) 0.8vcc 0.2vcc hld a td( f - hlda) tv( f - sync) (n cycles of f) hold th( f - hold) tsu(hold - f ) 0.8vcc 0.2vcc hld a tv( f - hlda) (enter state) (exit state) 0.5vcc 0.5vcc td( f - wr ) tv( f - wr)
3-16 6/2/98 timing requirements and switching characteristics 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 3-6. microprocessor and memory expansion mode timing diagram 2 figure 3-7. output switching characteristics measurement circuits ab15-ab8 ab7-ab0 rd, wr rdy db0-db7 (cpu read phase) db0-db7 (cpu write phase) 0.5vcc th(rd - rdy) tsu(rdy - rd) td(wr - db) tv(wr - db) tsu(db - rd) 0.5vcc 0.8vcc 0.2vcc 0.8vcc 0.2vcc 0.5vcc th(rd - db) twl(rd), twl(wr) tv(rd - ah) 0.5vcc tv(wr - ah) td(ah - rd) td(ah - wr) tv(rd - al) tv(wr - al) td(al - rd) td(al - wr) th(wr - rdy) tsu(rdy - wr) measurement output pin 100pf cmos output measurement output pin 100pf n-channel open-drain output 1k w
mitsubishi semiconductor america, inc. preliminary chapter 4 application notes 4.1 dmac . . . . . . . . . . . . . . . . 4-3 4.2 uart . . . . . . . . . . . . . . . . . 4-4 4.3 timer . . . . . . . . . . . . . . . . . 4-5 4.4 frequency synthesizer interface . . . . . . . . . . . . . . 4-6 4.5 usb transceiver . . . . . . . . 4-7 4.6 using the frequency synthesizer and dc-dc converter. . . . . . . . . . . . . . 4-8 4.7 ports . . . . . . . . . . . . . . . . 4-12 4.8 programming notes . . . . 4-13
4-2 8/10/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification dmac 8/10/98 4-3 4 application notes 4.1 dmac 4.1.1 application the following is an example of how to set up the dmac for interfacing with a peripheral block. in this case data is being transferred by dmac channel 0 from uart1 receive buffer to user ram. ? write 08 16 to dma0m1 so that after each transfer the destination register will be decremented by one and the source register will remain unchanged. ? write 00 16 to the low-order byte of the destination register (dma0dl) and 03 16 to the high-order byte of the destination register (dma0dh) so that the data received by the uart is placed in page three of the user ram starting from address 0300 16 . ? write 34 16 to the low-order byte of the source register (dma0sl) and 00 16 to the high-order byte of the source register (dma0sh) so that the dmac reads from address 0034 16 , which is the low- order byte of the uart receive buffer. ? write to the transfer count register (dma0cl/h) with a 16-bit value that corresponds to the number of transfers to occur before ?ag cruf and the dmac channel 0 interrupt are set. ? set the dmac transfer initiating source to the uart receive interrupt by writing 01 16 to dma0m2. ? place the uart in the desired con?guration for data reception by writing to the uart control (u1con), uart mode (u1mod), and uart baud rate (u1brg) registers. ? disable the uart receive interrupt from being serviced by the cpu by setting to a "0" bit 6 of interrupt control register a (icona). ? enable the dmac channel 0 interrupt by setting bit 4 of icona to "1". ? enable dmac channel 0 and reset the initiating source sample latch by writing c1 16 to dma0m2. the dma controller will transfer one byte of data from the uart receive buffer to third page user ram each time that the uart1 receive interrupt is set. because the destination register is incremented by one after each transfer, third page user ram is contiguously filled with received data. the transfer count register decrements by one after each transfer. when it underflows, flag d0uf and the dmac channel 0 interrupt are set. in the dmac channel 0 service routine, the user can either write new values to the source, destination, and transfer count registers, or leave these registers untouched. if they are left untouched, then they contain the previously written values that were reloaded when the transfer count register underflowed. this would result in the previously transferred uart data in third page user ram being overwritten with newly received uart data.
4-4 8/10/98 uart 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 4.2 uart 4.2.1 application ? 7 bit operation: when 7 bit data format is used, bit 7 of the transmit buffer register 1 is ignored. the transmit buffer regis- ter 2 does not affect the 7 or 8 bit format. ? 9 bit operation: the upper transmit/receive buffer register (uxtrb2) is a single bit register (bit 0). writing to the upper bits in these registers has no affect. when reading the register the upper 7 bits are "0". ? the rts control register (uxrtsc) is reset to 80 16 when the receive initialization bit (rin) is set to 1. when programming the rts delay, ensure the rin bit is set prior to programming the delay. note: the value in ubrg is not affected by a reset.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification timer 8/10/98 4-5 4.3 timer 4.3.1 usage ? if port 4 3 is read when timer x pulse output mode is being used, the value returned is the pulse output signal fed from the timer to the port. ? if port 4 4 is read when timer y pulse output mode is being used, the value returned is the pulse output signal fed from the timer to the port. ? if port 5 1 is read when timer1/timer2 pulse output mode is being used, the value returned is the pulse output signal fed from the timer to the port. table 4-1. initial values of timer pulse outputs timer selection bit initial output value timer y cntr1 polarity select bit (txm6) 0: logic h 1: logic l timer x cntr0 polarity select bit (txm6) 0: logic h 1: logic l timer 1/ timer 2 t out output active edge selection bit (t123m5) 0: logic h 1: logic l
4-6 8/10/98 frequency synthesizer interface 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 4.4 frequency synthesizer interface all passive components should be in close proximity to pin 18 (lpf). the recommended values are as follows: see figure 4-1 for a schematic of the lpf. figure 4-1. lpf filter schematic analog v ss and analog v dd , pins 19 and 17 should have isolated connectors to the digital v ss and v dd ground planes. figure 4-2 illustrates the power supply isolation. figure 4-2. power supply isolation table 4-2. recommended values r 000 w 1/8 watt 10% c2=680 pf 5 v 10% c1=0.1 m f 5 v 10% r c1 c2 pin 18 (lpf) pin 19 a vss digital v dd (on card) digital v ss analog v ss (pin 19) analog v dd (pin 17) c c decoupling capacitors ferrite beads
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification usb transceiver 8/10/98 4-7 4.5 usb transceiver when using the on-chip voltage converter to supply the necessary 3.3v to the driver circuit, a capacitor must be connected between ext. cap (pin 72) and v ss (pin 73). the capacitor spec is as follows: voltage: 5v, tolerance: 10%, type: mica, glass, polystyrene or low-loss ceramic. the recommended value of the capacitor on ext. cap is 2.2 m f in parallel with a 0.1 m f. the start-up time for this value of the capacitor is 3.2ms. the start-up time is approximately (1ms/ m f) + 1ms. after enabling the on-chip voltage converter, a certain amount of time must pass before a wit or stp instruction is executed. the amount of time is given by (c+1)ms, when c is the value in m f of the external capacitance connected to the ext. cap pin. for example, if the external capacitance is 2.2 m f, at least 3.2ms must elapse from the time that the on-chip voltage converter is enabled until a wit or stp instruction is executed. in order to meet the impedance matching requirements of the usb specification, a 33 w resistor must be added to usb d+ (pin 70) and to usb d- (pin 71). in addition, a 33pf capacitor should be connected between usb d+ and usb d- after the 33 w resistors. the placement of external components is illustrated in figure 4-3. figure 4-3. con?guration of external usb components 33 w 33 w + _ d+ d- xcv_vm_in xcv_vp_in xcv_rxd xcv_vp_out xcv_suspend xcv_vm_out xcv_txen_n transceiver usb_vp_out usb_txen_n usb_vm_out usb_suspend usb_rxd usb_vp_in usb_vm_in usb block voltage converter 2.2 m f 0.1 m f ext cap m37640e8 33 pf
4-8 8/10/98 using the frequency synthesizer and dc-dc converter 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 4.6 using the frequency synthesizer and dc-dc converter this section presents the recommended method of setting up and using the frequency synthesizer that generates the 48mhz clock needed by the usb fcu and the dc-dc converter that provides power to the d+/d- drivers. 4.6.1 reset of usb related registers figure 4-4. sfr reset venn diagram the special function registers (sfrs) that govern the operation of the frequency synthesizer, dc-dc converter and usb fcu are affected by one or more reset events. the addresses of the special function registers (sfrs) that are affected by hardware reset, usb reset, or both are shown in figure 4-4. all resettable sfrs, including sfrs and other registers internal to the usb fcu, are affected by a hardware reset, which occurs when the reset pin is brought low or an undefined opcode is fetched. see table 2.1 for a complete listing of sfrs and their reset values. only registers internal to the usb fcu are reset when a usb reset sent by the host/hub is detected. these usb registers are reset to their default values except for bit 5 of usbis2 (usb reset interrupt status flag), which is set to a 1. usb fcu registers are registers from address 0050 16 to 005e 16 and all other registers within the usb fcu, many of which the mcu does not have direct access to (e.g. fifo address pointers). the usb fifo registers are not reset. other sfrs such as usbc, fsc, and ccr are not affected by a usb reset. hardware reset usb reset sfr registers: 0000 16 to 0012 16 , 0014 16 to 001e 16 , 0013 16 (usbc), 001f 16 (ccr), 0020 16 to 004f 16 , 006d 16 to 006f 16 006c 16 (fsc), sfr registers: 0050 16 to 005e 16 (usb fcu registers)
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification using the frequency synthesizer and dc-dc converter 8/10/98 4-9 4.6.2 set up of frequency synthesizer and dc-dc converter figure 4-5. pll, dc-dc converter and usb functional block diagram a functional block diagram of the usb system on the m37640e8 which shows how the control signals affect operation is given in figure 4-5. 4.6.2.1 set up after hardware reset a hardware reset occurs when either the reset pin is brought low for more than 2 m s or an invalid opcode is fetched by the cpu. the frequency synthesizer (pll) and dc-dc converter should be set up as follows in the hardware reset routine (see figure 4-6): ? power up the m37640e8 and other components on the peripheral device for less than 100ma operation. the current limit only applies for bus powered devices. ? con?gure the pll for 48mhz f(vco) operation. ? enable the pll by setting fse (bit 0 of the frequency synthesizer control register (fsc)) to a 1, then wait for 2ms. ? check the lock status bit (ls, bit 7 of fsc). ? if the bit is a 1, go on. ? if the bit is a 0, wait 0.1ms longer and then re-check the bit. ? enable the dc-dc converter in high current mode by setting usbc4 (bit 4 of the usb control register (usbc)) to a 1 and keeping usbc3 (bit 3 of usbc) a 0. high current mode should always be used during normal usb operation. low current mode should only be used dur- ing a usb suspend. ? wait (c + 1)ms (where c equals the external capacitance connected to the ext cap pin in m f) for the voltage on ext cap to reach a steady state voltage of approximately 3.3v. (since the d+ pullup is connected to the ext cap pin, the upstream hub will detect that the peripheral device has been plugged in once the voltage on d+ reaches approximately 2.0v.) 33 w 33 w d+ d- usb fcu 2.2 m f 0.1 m f ext cap m37640e8 33 pf frequency synthesizer xin fse ls 1.5k w usb transceiver dc-dc converter usbc3 usbc4 usbc7 usbc7 usbc5 usbclk (48mhz) enable lock enable enable (enable) (enable) enable current mode
4-10 8/10/98 using the frequency synthesizer and dc-dc converter 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers example: a 2.3 m f capacitor connected to ext cap requires 3.3ms for the voltage on ext cap to be stable. ? enable the usb clock by setting usbc5 (bit 5 of usbc) to a "1". (if the usb clock and fcu are enabled before the voltage on ext cap is stable, a phantom usb reset may be detected, or the actual usb reset may not be detected.) ? wait at least 4 cycles of f , then enable the usb fcu by setting usbc7 (bit 7 of usbc) to a "1". ? enable other blocks as necessary. figure 4-6. pll and dc-dc converter set up timing after hardware reset 4.6.2.2 set up after usb reset signaling detected a usb reset is detected by the usb fcu when an se0 is present on d+/d- for at least 2.5 m s. detection of a usb reset results in bit 5 of usb interrupt status register 2 (usbis2) being set to a 1 and the registers within the usb fcu being reset to their default values. register usbc and the pll registers are not affected by a usb reset. a usb function interrupt request is also generated when the usb reset is detected. no modifications to the frequency synthesizer or dc-dc converter configuration should be made in the usb function interrupt routine. however, all usb fcu registers (addresses 0050 16 to 005f 16 ) must be reconfigured to their pre-enumeration state. 4.6.2.3 set up after usb suspend detected a usb suspend occurs if the usb fcu does not detect any bus activity on d+/d- for at least 3ms. detection of a suspend results in bit 7 of usbis2 being set to a 1. if bit 7 of the usb interrupt enable register 2 (usbie2) is a 1, a usb function interrupt request is also generated. the configuration of the frequency synthesizer and dc-dc converter should be changed as follows in the usb function interrupt routine (if the device is bus powered): ? disable the usb clock by setting usbc5 (bit 5 of usbc) to a "0". ? disable the pll by setting fse (bit 0 of fsc) to a "0". reset fse ls usbc4 usbc5 usbc7 wait 2ms wait (c+1)ms enable pll enable dc-dc converter enable usb clock enable usb fcu wait at least 4 cycles of f
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification using the frequency synthesizer and dc-dc converter 8/10/98 4-11 ? change the dc-dc converter from high current mode to low current mode by setting usbc3 (bit 3 of the usbc) to a 1. ? perform other tasks to reduce total current to below 500ua. ? execute the stp instruction. make sure to enable the usb suspend/resume signaling interrupt enable bit (bit 7 of usbie2 = 1), the usb function interrupt (bit 0 of ireqa = 1) and clear the i ?ag prior to executing the stp instruction so the mcu can wake up once resume sig- naling is detected. note that no action may be necessary if the device is self powered. 4.6.2.4 set up after usb resume signaling detected a resume occurs when the usb fcu is in the suspend state and detects non-idle signaling on d+/d-. detection of a resume results in bit 6 of usbis2 being set to a 1. if bit 7 of usbie2 is a 1, a usb function interrupt request is also generated. if the mcu was in the stop state prior to the detection of the resume, the usb function interrupt request will cause the mcu to wake up from the stop state. see section 2.16.1 stop mode for details on waking up from the stop state. the configuration of the frequency synthesizer and dc-dc converter should be changed as follows in the usb function interrupt routine (if the device is bus powered): ? change the dc-dc converter from low current mode to high current mode by setting usbc3 (bit 3 of the usbc) to a 0. ? re-enable the pll for 48mhz f(vco) by setting fse (bit 0 of the fsc) to a 1, then wait for 2ms. ? check the lock status bit (ls, bit 7 of fsc). ? if the bit is a 1, go on. ? if the bit is a 0, wait 0.1ms longer and then re-check the bit. ? enable the usb clock by setting usbc5 (bit 5 of usbc) to a "1". ? enable other blocks as necessary. note that the configuration changes described above may not need to be made if the mcu was not placed in a suspend state as described in section 4.6.2.3 "set up after usb suspend detected".
4-12 8/10/98 ports 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers 4.7 ports after reset, port 2 input voltage characteristics are set to 0.5vcc for v ih and 0.16vcc for v il . to change the input voltage characteristics to cmos levels, set bit 6 of the port control register (ptc) to a 1.
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification programming notes 8/10/98 4-13 4.8 programming notes always execute an sei instruction immediately before executing a plp instruction.
4-14 8/10/98 programming notes 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers
mitsubishi semiconductor america, inc. preliminary chapter 5 sfr register list 5 register list . . . . . . . . . . . . . . . . . 5-3
5-2 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-3 5 register list figure 5-1. cpu mode register a figure 5-2. cpu mode register b cpma0,1 processor mode bits (bits 1,0) bit 1 bit 0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode 1 1: not used cpma2 stack page selection bit (bit 2) 0: in page 0 area 1: in page 1 area cpma3 x cout drive capacity selection bit (bit 3) 0: low 1: high cpma4 clock xc in -xc out stop bit (bit 4) 0: stop 1: oscillator cpma5 clock x in -x out stop bit (bit 5) 0: oscillator 1: stop cpma6 internal clock selection bit (bit 6) 0: external clock 1: f syn cpma7 external clock selection bit (bit 7) 0: x in -x out 1: xc in -xc out msb 7 lsb 0 cpma7 cpma6 cpma5 cpma4 cpma3 cpma2 cpma1 cpma0 access: r/w reset: 0c 16 address: 0000 16 cpmb0,1 slow memory wait bits (bits 1,0) bit 1 bit 0 0 0: no wait 0 1: one time wait 1 0: two time wait 1 1: three time wait cpmb2,3 slow memory mode bit (bits 3,2) bit 3 bit 2 0 0: software wait 0 1: not used 1 0: fixed wait by rdy pin l 1 1: extended rdy wait cpmb4 expanded data memory access bit (bit 4) 0: edma output disabled (64 kbyte data access area) 1: edma output enabled (greater than 64 kbytes data access area) cpmb5 hold function enable bit (bit 5) 0: hold function disabled 1: hold function enabled cpmb6 reserved (read/write 0) cpmb7 x out drive capacity selection bit (bit 7) 0: low 1: high (default state after reset and after stop mode) access: r/w reset: 83 16 address: 0001 16 msb 7 lsb 0 cpmb4 cpmb3 cpmb2 cpmb1 cpmb0 cpmb7 reserved cpmb5
5-4 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-3. ireqa con?guration figure 5-4. ireqb con?guration figure 5-5. ireqc con?guration figure 5-6. icona con?guration ira0 usb function interrupt request (bit 0) ira1 usb sof interrupt request (bit 1) ira2 external interrupt 0 request (bit 2) ira3 external interrupt 1 request (bit 3) ira4 dmac channel 0 interrupt request (bit 4) ira5 dmac channel 1 interrupt request (bit 5) ira6 uart1 receive buffer full interrupt request (bit 6) ira7 uart1 transmit interrupt request (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 ira7 ira6 ira5 ira4 ira3 ira2 ira1 ira0 access: r/w reset: 00 16 address: 0002 16 irb0 uart1 error sum interrupt request (bit 0) irb1 uart2 receive buffer full interrupt request (bit 1) irb2 uart2 transmit interrupt request (bit 2) irb3 uart2 error sum interrupt request (bit 3) irb4 timer x interrupt request (bit 4) irb5 timer y interrupt request (bit 5) irb6 timer 1 interrupt request (bit 6) irb7 timer 2 interrupt request (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 irb7 irb6 irb5 irb4 irb3 irb2 irb1 irb0 access: r/w reset: 00 16 address: 0003 16 irc0 timer 3 interrupt request (bit 0) irc1 external cntr0 interrupt request (bit 1) irc2 external cntr1 interrupt request (bit 2) irc3 sio interrupt request (bit 3) irc4 input buffer full interrupt request (bit 4) irc5 output buffer empty interrupt request (bit 5) irc6 key-on wake-up interrupt request (bit 6) 0: no interrupt request issued 1: interrupt request issued bit 7 reserved (read/write 0) msb 7 lsb 0 reserved irc6 irc5 irc4 irc3 irc2 irc1 irc0 access: r/w reset: 00 16 address: 0004 16 ica0 usb function interrupt enable (bit 0) ica1 usb sof interrupt enable (bit 1) ica2 external interrupt 0 enable (bit 2) ica3 external interrupt 1 enable (bit 3) ica4 dmac channel 0 interrupt enable (bit 4) ica5 dmac channel 1 interrupt enable (bit 5) ica6 uart1 receive buffer full interrupt enable (bit 6) ica7 uart1 transmit interrupt enable (bit 7) 0: interrupt disable 1: interrupt enable msb 7 lsb 0 ica7 ica6 ica5 ica4 ica3 ica2 ica1 ica0 access: r/w reset: 00 16 address: 0005 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-5 figure 5-7. iconb con?guration figure 5-8. iconc con?guration figure 5-9. port control register icc0 uart1 error sum interrupt enable (bit 0) icc1 uart2 receive buffer full interrupt enable (bit 1) icc2 uart2 transmit interrupt enable (bit 2) icc3 uart2 error sum interrupt enable (bit 3) icc4 timer x interrupt enable (bit 4) icc5 timer y interrupt enable (bit 5) icc6 timer 1 interrupt enable (bit 6) icc7 timer 2 interrupt enable (bit 7) 0: interrupt disable 1: interrupt enable msb 7 lsb 0 icb7 icb6 icb5 icb4 icb3 icb2 icb1 icb0 access: r/w reset: 00 16 address: 0006 16 icc0 timer 3 interrupt enable (bit 0) icc1 external cntr0 interrupt enable (bit 1) icc2 external cntr1 interrupt enable (bit 2) icc3 sio interrupt enable (bit 3) icc4 input buffer full interrupt enable (bit 4) icc5 output buffer empty interrupt enable (bit 5) icc6 key-on wake-up interrupt enable (bit 6) 0: interrupt disabled 1: interrupt enabled bit 7 reserved (read/write 0) msb 7 lsb 0 reserved icc6 icc5 icc4 icc3 icc2 icc1 icc0 access: r/w reset: 00 16 address: 0007 16 msb 7 lsb 0 ptc4 ptc3 ptc2 ptc1 ptc0 ptc0 slew rate control bit ports 0-3 (bit 0) 0: disabled 1: enabled ptc1 slew rate control bit port 4 (bit 1) 0: disabled 1: enabled ptc2 slew rate control bit port 5 (bit 2) 0: disabled 1: enabled ptc3 slew rate control bit port 6 (bit 3) 0: disabled 1: enabled ptc4 slew rate control bit port 7 (bit 4) 0: disabled 1: enabled ptc5 slew rate control bit port 8 (bit 5) 0: disabled 1: enabled ptc6 port 2 input level select bit (bit 6) 0: reduced vihl level input 1: cmos level input ptc7 master bus input level select bit (bit 7) 0: cmos level input 1: ttl level input access: r/w reset: 00 16 ptc7 ptc6 ptc5 address: 0010 16
5-6 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-10. ipol con?guration figure 5-11. pull-up control register figure 5-12. usb control register int0 pol int0 interrupt edge selection bit 0: falling edge selected. 1: rising edge selected. int1 pol int1 interrupt edge selection bit 0: falling edge selected. 1: rising edge selected. bits 2-7 reserved (read/write 0) msb 7 lsb 0 int1 pol int0 pol access: r/w reset: 00 16 address: 0011 16 reserved reserved reserved reserved reserved reserved pup2 0 pull-up control for port 2 (bit 0) 0: disabled 1: enabled pup2 1 pull-up control for port 2 (bit 1) 0: disabled 1: enabled pup2 2 pull-up control for port 2 (bit 2) 0: disabled 1: enabled pup2 3 pull-up control for port 2 (bit 3) 0: disabled 1: enabled pup2 4 pull-up control for port 2 (bit 4) 0: disabled 1: enabled pup2 5 pull-up control for port 2 (bit 5) 0: disabled 1: enabled pup2 6 pull-up control for port 2 (bit 6) 0: disabled 1: enabled pup2 7 pull-up control for port 2 (bit 7) 0: disabled 1: enabled msb 7 lsb 0 pup2 4 pup2 3 pup2 2 pup2 1 pup2 0 access: r/w reset: 00 16 pup2 7 pup2 6 pup2 5 address: 0012 16 bit 0 reserved (read/write 0) usbc1 usb default state selection bit (bit 1) 0: in default state after powerup/reset 1: in default state after received the usb reset signaling bit 2 reserved (read/write 0) usbc3 transceiver voltage converter high/low current mode selection bit (bit 3) 0: high current mode 1: low current mode usbc4 usb transceiver voltage converter enable bit (bit 4) 0: usb transceiver voltage converter disabled 1: usb transceiver voltage converter enabled usbc5 usb clock enable bit (bit 5) 0: 48 mhz clock to the usb block is disabled. 1: 48 mhz clock to the usb block is enabled. usbc6 usb sof port select bit (bit 6) 0: usb sof output is disabled. p7 0 is used as gpio pin. 1: usb sof output is enabled usbc7 usb enable bit (bit 7) 0: usb block is disabled, all usb internal registers are held at their default values. 1: usb block is enabled msb 7 lsb 0 usbc7 usbc6 usbc5 usbc4 usbc3 usbc1 reserved access: r/w reset: 00 16 address: 0013 16 reserved
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-7 figure 5-13. clock control register figure 5-14. txm register bits 0-3 reserved (read/write 0) ccr4: pll bypass bit (bit 4) 0: f usb = f vco (frequency synthesizer output) 1: f usb = f xin ccr5: xc out oscillation drive disable bit (bit 5) 0: xc out oscillation drive is enabled (when xc in oscillation is enabled). 1: xc out oscillation drive is disabled. ccr6: x out oscillation drive disable bit (bit 6) 0: x out oscillation drive is enabled (when x in oscillation is enabled). 1: x out oscillation drive is disabled. ccr7: x in divider select bit (bit 7) 0: f xin /2 is used for the system clock source when cmpa7:6=00 1: f xin is used for the system clock source when cmpa7:6=00 msb 7 lsb 0 reserved reserved reserved access: r/w reset: 00 16 reserved address: 001f 16 ccr4 ccr7 ccr6 ccr5 txm0 timer x data write control bit (bit 0) 0: write data in latch and timer 1: write data in latch only txm2,1 timer x frequency division ratio bits (bits 2,1) bit 2 bit 1 00: f divided by 8 01: f divided by 16 10: f divided by 32 11: f divided by 64 txm3 timer x internal clock select (bit 3) 0: f /n 1: scsgclk (from chip special count source generator) txm5,4 timer x mode bits (bits 5,4) bit 5 bit 4 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode txm6 cntr0 polarity select bit (bit 6) 0: for event counter mode, clocked by rising edge for pulse output mode, start from high level output for cntr0 interrupt request, falling edge active for pulse width measurement mode, measure high period 1: for event counter mode, clocked on falling edge for pulse output mode, start from low level output for cntr0 interrupt request, rising edge active for pulse width measurement mode, measure low period txm7 timer x stop bit (bit 7) 0: count start 1: count stop msb 7 lsb 0 txm7 txm6 txm5 txm4 txm3 txm2 txm1 txm0 access: r/w reset: 00 16 address: 0027 16
5-8 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-15. tym register figure 5-16. t123m register msb 7 lsb 0 tym7 tym6 tym5 tym4 tym3 tym2 tym1 tym0 tym0 timer y data write control bit (bit 0) 0: write data in latch and timer 1: write data in latch only tym1 timer y output control bit (bit 1) 0: tyout output disable 1: tyout output enable tym3,2 timer y frequency division ratio bits (bit 3,2) bit 2 bit 1 00: f divided by 8 01: f divided by 16 10: f divided by 32 11: f divided by 64 tym5,4 timer y mode bits (bits 5,4) bit 2 bit 1 0 0: timer mode 0 1: pulse period measurement mode 1 0: event counter mode 1 1: hl pulse width measurement mode (continuously measures high period and low period) tym6 cntr1 polarity select bit (bit 6) 0: for event counter mode, clocked by rising edge for pulse period measurement mode, falling edge detection for cntr1 interrupt request, falling edge active for tyout, start on high output 1: for event counter mode, clocked on falling edge for pulse period measurement mode, rising edge detection for cntr1 interrupt request, rising edge active for tyout, start on low output tym7 timer y stop bit (bit 7) 0: count start 1: count stop access: r/w reset: 00 16 address: 0028 16 t123m0 tout source selection bit (bit 0) 0: tout = timer 1 output 1: tout = timer 2 output t123m1 timer 1 stop bit (bit 1) 0: timer running 1: timer stopped t123m2 timer 1 count source select bit (bit 2) 0: f divided by 8 1: xcin divided by 2 t123m3 timer 2 count source select bit (bit 3) 0: timer 1 under?ow signal 1: f t123m4 timer 3 count source select bit (bit 4) 0: timer 1 under?ow signal 1: f divided by 8 t123m5 tout output active edge selection bit (bit 5) 0: start on high output 1: start on low output t123m6 tout output control bit (bit 6) 0: tout output disabled 1: tout output enabled t123m7 timer 1 and 2 data write control bit (bit 7) 0: write data in latch and timer 1: write data in latch only msb 7 lsb 0 t123m7 t123m6 t123m5 t123m4 t123m3 t123m1 t123m0 access: r/w reset: 00 16 t123m2 address: 0029 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-9 figure 5-17. sio control register 1 figure 5-18. sio control register 2 figure 5-19. scsgm register msb 7 lsb 0 scsel tdsel rdysel psel iscsel1 iscsel0 iscsel0-2 internal synchronization clock select bits (bits 2,1,0) bit 2 bit 1 bit 0 0 0 0: internal clock divided by 2. 0 0 1: internal clock divided by 4. 0 1 0: internal clock divided by 8. 0 1 1: internal clock divided by 16. 1 0 0: internal clock divided by 32. 1 0 1: internal clock divided by 64. 1 1 0: internal clock divided by 128. 1 1 1: internal clock divided by 256. psel sio port selection bit (bit 3) 0: i/o port 1: txd output, sclk function rdysel srd y output select bit (bit 4) 0: i/o port 1: srd y signal tdsel transfer direction select bit (bit 5) 0: lsb ?rst 1: msb ?rst scsel synchronization clock select bit (bit 6) 0: external clock 1: internal clock ochcont txd output channel control bit (bit 7) 0: cmos output 1: n-channel open drain output access: r/w reset: 00 16 iscsel2 ochcont address: 002b 16 slave slave mode selection bit (bit 0) 0: normal mode 1: slave mode (to enter slave mode, bit 4 of sio control register 1 also needs to be set) clksel sio internal clock selection bit (bit 1) 0: f 1: scsgclk rxdsel srxd input selection bit (bit 2) 0: srxd input disabled 1: srxd input enabled bits 3-4 reserved (read/write 1) bits 5-7 reserved (read/write 0) msb 7 lsb 0 clksel slave access: r/w reset: rxdsel reserved address: 002c 16 reserved reserved reserved reserved 18 16 msb 7 lsb 0 scsgm3 scsgm1 scsgm0 scsgm0 scsg1 data write control bit (bit 0) 0: write data in latch and timer 1: write data in latch only scsgm1 scsg1 count stop bit (bit 1) 0: count start 1: count stop scsgm2 scsg2 data write control bit (bit 2) 0: write data in latch and timer 1: write data in latch only scsgm3 scsgclk output control bit (bit 3) 0: scsgclk output disabled (scsg1 and scsg2 off) 1: scsgclk output enabled. bits 4-7 reserved (read/write 0) access: r/w reset: 00 16 scsgm2 address: 002f 16 reserved reserved reserved reserved
5-10 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-20. uxmod register figure 5-21. uxsts register msb 7 lsb 0 le1 le0 pen pmd stb ps0 clk clk uart clock selection bit (bit 0) 0: f 1: scsgclk ps1,0 internal clock prescaling selection bits (bits 2,1) bit 2 bit 1 0 0: division by 1 0 1: division by 8 1 0: division by 32 1 1: division by 256 stb stop bits selection bit (bit 3) 0: 1 1: 2 pmd parity selection bit (bit 4) 0: even 1: odd pen parity enable bit (bit 5) 0: off 1: on le1,0 uart character length selection bits (bits 7,6) bit 7 bit 6 0 0: 7 bits/character 0 1: 8 bits/character 1 0: 9 bits/character 1 1: reserved access: r/w reset: 00 16 ps1 address: 0030 16 , 0038 16 msb 7 lsb 0 ser oer fer per tbe tcm tcm transmit-complete (transmission register empty) flag (bit 0) 0: data in the transmission register. 1: no data in the transmission register. tbe tx buffer empty flag (bit 1) 0: data in the tx buffer. 1: no data in the tx buffer. rbf rx buffer full flag (bit 2) 0: no data in the rx buffer. 1: data in the rx buffer. per receive parity error flag (bit 3) 0: no receive parity error. 1: receive parity error. fer receive framing error flag (bit 4) 0: no receive framing error. 1: receive framing error. oer receive overrun flag (bit 5) 0: no receive overrun. 1: receive overrun. ser receive error sum flag (bit 6) 0: no receive error. 1: receive error. bit 7 reserved (read 0) access: r only reset: 03 16 rbf address: 0032 16 , 003a 16 reserved
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-11 figure 5-22. uxcon register figure 5-23. uxrtsc register msb 7 lsb 0 ame tis rin ren ten ten transmission enable bit (bit 0) 0: disable the transmit process 1: enables the transmit process. if the transmit process is disabled (ten cleared) during transmission, the transmit will not stop until completed. ren receive enable bit (bit 1) 0: disable the receive process 1: enables the receive process. if the receive process is disabled (ren cleared) during reception, the receive will not stop until completed. tin transmission initialization bit (bit 2) 0: no action. 1: resets the uart transmit status register bits as well as stopping the transmission operation. the ten bit must be set and the transmit buffer reloaded in order to transmit again. the tin is automatically reset one cycle after tin is set. rin receive initialization bit (bit 3) 0: no action. 1: clears the uart receive status ?ags and the ren bit. if rin is set during receive in progress, receive operation is aborted. the rin bit is automatically reset one cycle after rin is set. tis transmit interrupt source selection bit (bit 4) 0: transmit interrupt occurs when the transmit buffer empty ?ag is set. 1: transmit interrupt occurs when the transmit complete ?ag is set. cts_sel clear-to-send ( cts) enable bit (bit 5) 0: cts function is disabled, p8 6 (or p8 2 ) is used as gpio pin. 1: cts function is enabled, p8 6 (or p8 2 ) is used as cts input. rts_sel request-to-send ( r ts) enable bit (bit 6) 0: rts function is disabled, p8 7 (or p8 3 ) is used as gpio pin. 1: rts function is enabled, p8 7 (or p8 3 ) is used as r ts output. ame uart address mode enable bit (bit 7) 0: address mode disabled. 1: address mode enabled. access: r/w reset: 00 16 rts_sel cts_sel tin address: 0033 16 ,003b 16 msb 7 lsb 0 rts2 rts1 rts0 bits 0-3 reserved (read/write 0) rts3:0 rts assertion delay count 3:0 (bits 7,6,5,4) 0000: no delay, r ts asserts immediately after receive operation completes. 0001: r ts asserts 8 bit-times after receive operation completes. 0010: r ts asserts 16 bit-times after receive operation completes. 0011: r ts asserts 24 bit-times after receive operation completes. . . . 1000: r ts asserts 64 bit-times after receive operation completes. . . . 1110: r ts asserts 112 bit-times after receive operation completes. 1111: r ts asserts 120 bit-times after receive operation completes. access: r/w reset: 80 16 rts3 address: 0036 16 , 003e 16 reserved reserved reserved reserved
5-12 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-24. dmais con?guration figure 5-25. dmaxm1 con?guration d0uf dmac channel 0 count register under?ow flag (bit 0) 0: channel 0 transfer count register under?ow has not occurred 1: channel 0 transfer count register under?ow has occurred d0sfi dmac channel 0 suspend (due to interrupt service request) flag (bit 1) 0: channel 0 transfer has not been suspended 1: channel 0 transfer has been suspended d1uf dmac channel 1 count register under?ow flag (bit 2) 0: channel 1 transfer count register under?ow has not occurred 1: channel 1 transfer count register under?ow has occurred d1sfi dmac channel 1 suspend (due to interrupt service request) flag (bit 3) 0: channel 1 transfer has not been suspended 1: channel 1 transfer has been suspended dtsc dmac transfer suspend control bit (bit 4) 0: only burst transfers are suspended during interrupt servicing 1: both burst and single-byte transfers are suspended during interrupt servicing drldd dmac register reload disable bit (bit 5) 0: reload of source and destination registers of both channels enabled 1: reload of source and destination registers of both channels disabled bit 6 reserved (read/write 0) dci channel index bit (bit 7) 0: channel 0 mode, source, destination, and transfer count registers accessible 1: channel 1 mode, source, destination, and transfer count registers accessible msb 7 lsb 0 dci reserved drldd dtsc d1sfi d1uf d0sfi d0uf access: r/w reset: 00 16 address: 003f 16 msb 7 lsb 0 dxtms dxrld dxdaue dxdwc dxdrce dxdrid dxsrce dxsrid dxsrid dmac channel x source register increment/decrement select bit (bit 0) 0: increment after transfer 1: decrement after transfer dxsrce dmac channel x source register increment/decrement enable bit (bit 1) 0: increment/decrement disabled (no change after transfer) 1: increment/decrement enabled dxdrid dmac channel x destination register increment/decrement select bit (bit 2) 0: increment after transfer 1: decrement after transfer dxdrce dmac channel x destination register increment/decrement enable bit (bit 3) 0: increment/decrement disabled (no change after transfer) 1: increment/decrement enabled dxdwc dmac channel x data write control bit (bit 4) 0: write data in reload latches and registers 1: write data in reload latches only dxdaue dmac channel x disable after count register under?ow enable bit (bit 5) 0: channel x not disabled after count register under?ow 1: channel x disabled after count register under?ow dxrld dmac channel x register reload bit (bit 6) 0: no action (bit is always read as 0) 1: setting to 1 causes the source, destination, and transfer count registers of channel x to be reloaded dxtms dmac channel x transfer mode selection bit (bit 7) 0: single-byte transfer mode 1: burst transfer mode access: r/w reset: 00 16 address: 0040 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-13 figure 5-26. dma0m2 con?guration figure 5-27. dma1m2 con?guration msb 7 lsb 0 d0cen d0crr d0umie d0swt d0hrs3 d0hrs2 d0hrs1 d0hrs0 d0hrs3,2,1,0 dmac channel 0 hardware transfer request source bits (bits 3, 2, 1, 0) 0000: disabled 0001: uart1 receive interrupt 0010: uart1 transmit interrupt 0011: timery interrupt 0100: external interrupt 0 0101: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0110: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0111: usb endpoint 3 in_pkt_rdy signal (falling edge active) 1000: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1001: usb endpoint 1 out_fifo_not_empty signal (rising edge active) 1010: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1011: usb endpoint 3 out_pkt_rdy signal (rising edge active) 1100: mbi obe 0 signal (rising edge active) 1101: mbi ibf 0 (data) signal (rising edge active) 1110: sio receive/transmit interrupt 1111: cntr1 interrupt d0swt dmac channel 0 software transfer trigger (bit 4) 0: no action (bit is always read as 0) 1: writing 1 requests a channel 0 transfer d0umie dmac channel 0 usb and mbi enable bit (bit 5) 0: disabled 1: enabled d0crr dmac channel 0 transfer initiation source capture register reset (bit 6) 0: no action (bit is always read as 0) 1: setting to 1 causes reset of the channel 0 capture register d0cen dmac channel 0 enable bit (bit 7) 0: channel 0 disabled 1: channel 0 enabled access: r/w reset: 00 16 address: 0041 16 d1hrs3,2,1,0 dmac channel 1hardware transfer request source bits (bits 3, 2, 1, 0) 0000: disabled 0001: uart2 receive interrupt 0010: uart2 transmit interrupt 0011: timerx interrupt 0100: external interrupt 1 0101: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0110: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0111: usb endpoint 4 in_pkt_rdy signal (falling edge active) 1000: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1001: usb endpoint 1 out_fifo_not_empty signal(rising edge active) 1010: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1011: usb endpoint 4 out_pkt_rdy signal (rising edge active) 1100: mbi obe1 signal (rising edge active) 1101: mbi ibf1(data) signal (rising edge active) 1110: timer1 interrupt 1111: cntr0 interrupt d1swt dmac channel 1 software transfer trigger (bit 4) 0: no action (bit is always read as 0) 1: writing 1 requests a channel 0 transfer d1umie dmac channel 1 usb and mbi enable bit (bit 5) 0: disabled 1: enabled d1crr dmac channel 1 transfer initiation source capture register reset (bit 6) 0: no action (bit is always read as 0) 1: setting to 1 causes reset of the channel 1 capture register d1cen dmac channel 1 enable bit (bit 7) 0: channel 1 disabled 1: channel 1 enabled msb 7 lsb 0 d1cen d1crr d1umie d1swt d1hrs3 d1hrs2 d1hrs1 d1hrs0 access: r/w reset: 00 16 address: 0041 16
5-14 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-28. data bus buffer status register 0 figure 5-29. data bus buffer control register 0 figure 5-30. data bus buffer status register 1 dbbs00 output buffer full (obf 0 ) flag (bit 0) 0: output buffer empty. 1: output buffer full. dbbs01 input buffer full (ibf 0 ) flag (bit 1) 0: input buffer empty. 1: input buffer full. dbbs02 user de?nable (u2) flag (bit 2) dbbs03 a 0 (a 00 ) flag (bit 3) indicates the a 0 status when ibf ?ag is set dbbs04 user de?nable (u4) flag (bit 4) dbbs05 user de?nable (u5) flag (bit 5) dbbs06 user de?nable (u6) flag (bit 6) dbbs07 user de?nable (u7) flag (bit 7) msb 7 lsb 0 dbbs06 dbb05 dbbs04 dbbs03 dbbs01 dbbs00 access: r/w reset: 00 16 dbbs02 dbbs07 address: 0049 16 dbbc00 obf output selection bit (bit 0) 0: p5 2 pin is operated as gpio 1: p5 2 pin is operated as obf 0 output pin dbbc01 ibf output selection bit (bit 1) 0: p5 3 pin is operated as gpio 1: p5 3 pin is operated as ibf 0 output pin dbbc02 ibf 0 interrupt selection bit (bit 2) 0: ibf 0 interrupt is generated by both write-data (a 0 = 0) and write-command (a 0 = 1) 1: ibf 0 interrupt is generated by write-command (a 0 = 1) only dbbc03 output buffer 0 empty interrupt disable bit (bit 3) 0: enabled 1: disabled dbbc04 input buffer 0 full interrupt disable bit (bit 4) 0: enabled 1: disabled dbbc05 reserved (read/write 0) dbbc06 master cpu bus interface enable bit (bit 6) 0: p6 0 -p6 7 , p5 4 -p5 7 are gpio pins 1: p6 0 -p6 7 , p5 4 -p5 7 are bus interface signals dq0-dq7, s 0 , a 0 , r, w respectively. dbbc07 bus interface type selection bit (bit 7) 0: rd, wr separate type bus 1: r/w type bus. msb 7 lsb 0 dbbc06 dbbc01 dbbc00 access: r/w reset: 00 16 dbbc02 dbbc07 address: 004a 16 dbbc03 dbbc04 reserved msb 7 lsb 0 dbbs16 dbb15 dbbs14 dbbs13 dbbs11 dbbs10 dbbs10 output buffer full (obf 1 ) flag (bit 0) 0: output buffer empty. 1: output buffer full. dbbs11 input buffer full (ibf 1 ) flag (bit 1) 0: input buffer empty. 1: input buffer full. dbbs12 user de?nable (u2) flag (bit 3) dbbs13 a 0 (a 01 ) flag (bit 2) indicates the a 0 status when ibf ?ag is set dbbs14 user de?nable (u4) flag (bit 4) dbbs15 user de?nable (u5) flag (bit 5) dbbs16 user de?nable (u6) flag (bit 6) dbbs17 user de?nable (u7) flag (bit 7) access: r/w reset: 00 16 dbbs12 dbbs17 address: 004d 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-15 figure 5-31. data bus buffer control register 1 figure 5-32. function address register figure 5-33. power management register figure 5-34. interrupt status register 1 dbbc10 obf 1 output selection bit (bit 0) 0: p7 4 pin is operated as gpio 1: p7 4 pin is operated as obf 1 output pin if dbbc17 = 1 dbbc11 ibf 1 output selection bit (bit 1) 0: p7 3 pin is operated as gpio 1: p7 3 pin is operated as ibf 1 output pin if dbbc17 = 1 dbbc12 ibf 1 interrupt selection bit (bit 2) 0: ibf 1 interrupt is generated by both write-data (a 0 = 0) and write-command (a 0 = 1) 1: ibf 1 interrupt is generated by write-command (a 0 = 1) only dbbc13 output buffer 1 empty interrupt disable bit (bit 3) 0: enabled 1: disabled dbbc14 input buffer 1 full interrupt disable bit (bit 4) 0: enabled 1: disabled dbbc15 reserved (read/write 0) dbbc16 reserved (read/write 0) dbbc17 data bus buffer function selection bit (bit 7) 0: single data bus buffer - p7 2 is used as gpio 1: double data bus buffer - p7 2 is used as s 1 input msb 7 lsb 0 dbbc11 dbbc10 access: r/w reset: 00 16 dbbc12 dbbc17 address: 004e 16 reserved dbbc13 dbbc14 reserved funad6:0 7-bit programmable function address (bits 6-0) bit 7 reserved (read/write 0) msb 7 lsb 0 reserved funad6 funad5 funad4 funad3 funad1 funad0 access: r/w reset: 00 16 funad2 address: 0050 16 suspend usb suspend detection flag (bit 0) (write 0 only or read) 0: no usb suspend signal detected 1: usb suspend signal detected resume usb resume detection flag (bit 1) (write 0 only or read) 0: no usb resume signal detected 1: usb resume signal detected wakeup usb remote wake-up bit (bit 2) 0: end remote resume signaling 1: remote resume signaling (if suspend = 1) bit7:3 reserved (read/write 0) msb 7 lsb 0 reserved reserved reserved reserved reserved resume suspend access: r/w reset: 00 16 wakeup address: 0051 16 intst0 usb endpoint 0 interrupt status flag (bit 0) bit 1 reserved (read/write 0) intst2 usb endpoint 1 in interrupt status flag (bit 2) intst3 usb endpoint 1 out interrupt status flag (bit 3) intst4 usb endpoint 2 in interrupt status flag (bit 4) intst5 usb endpoint 2 out interrupt status flag (bit 5) intst6 usb endpoint 3 in interrupt status flag (bit 6) intst7 usb endpoint 3 out interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 intst7 intst6 intst5 intst4 intst3 reserved intst0 access: r/w reset: 00 16 intst2 address: 0052 16
5-16 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-35. interrupt status register 2 figure 5-36. interrupt enable register 1 figure 5-37. interrupt enable register 2 figure 5-38. frame number register low figure 5-39. frame number register high intst8 usb endpoint 4 in interrupt status flag (bit 0) intst9 usb endpoint 4 out interrupt status flag (bit 1) bit 3:2 reserved (read/write 0) intst12 usb overrun/underrun interrupt status flag (bit 4) intst13 usb reset interrupt status flag (bit 5) intst14 usb resume signaling interrupt status flag (bit 6) intst15 usb suspend signaling interrupt status flag (bit 7) 0: no interrupt request issued 1: interrupt request issued msb 7 lsb 0 intst15 intst14 intst13 intst12 reserved intst9 intst8 access: r/w reset: 00 16 address: 0053 16 reserved inten0 usb endpoint 0 in interrupt enable bit (bit 0) bit 1 reserved (read/write 0) inten2 usb endpoint 1 in interrupt enable bit (bit 2) inten3 usb endpoint 1 out interrupt enable bit (bit 3) inten4 usb endpoint 2 in interrupt enable bit (bit 4) inten5 usb endpoint 2 out interrupt enable bit (bit 5) inten6 usb endpoint 3 in interrupt enable bit (bit 6) inten7 usb endpoint 3 out interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled msb 7 lsb 0 inten7 inten6 inten5 inten4 inten3 reserved inten0 access: r/w reset: ff 16 inten2 address: 0054 16 inten8 usb endpoint 4 in interrupt enable bit (bit 0) inten9 usb endpoint 4 out interrupt enable bit (bit 1) bit 3:2 reserved (read/write 0) inten12 usb overrun/underrun interrupt enable bit (bit 4) inten13 usb reset interrupt enable bit (bit 5) bit 6 reserved (read/write 0) inten15 usb suspend/resume signaling interrupt enable bit (bit 7) 0: interrupt disabled 1: interrupt enabled msb 7 lsb 0 inten15 reserved inten13 inten12 reserved inten9 inten8 access: r/w reset: 33 16 address: 0055 16 reserved fn7:0 lower 8 bits of the 11-bit frame number issued with a sof token msb 7 lsb 0 fn7 fn6 fn5 fn4 fn3 fn1 fn0 access: r reset: 00 16 fn2 address: 0056 16 fn10:8 upper 3 bits of the 11-bit frame number issued with a sof token bits 7:3 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved fn9 fn8 access: r reset: 00 16 fn10 address: 0057 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-17 figure 5-40. endpoint index register figure 5-41. endpoint 0 in csr epindx2:0 endpoint index: bit 2 bit 1 bit 0 0 0 0: function endpoint 0 0 0 1: function endpoint 1 0 1 0: function endpoint 2 0 1 1: function endpoint 3 1 0 0: function endpoint 4 others: unde?ned bits 3:5 reserved (read/write 0) auto_fl auto_flush bit (bit 6) 0: hardware auto fifo ?ush disabled 1: hardware auto fifo ?ush enabled iso_upd iso_update bit (bit 7) 0: iso_update disabled 1: iso_update enabled msb 7 lsb 0 iso_upd auto_fl reserved reserved reserved epindx1 epindx0 access: r/w reset: 00 16 epindx2 address: 0058 16 in0csr0 out_pkt_rdy flag (bit 0) (read only - write 0) 0: out packet is not ready 1: out packet is ready in0csr1 in_pkt_rdy bit (bit 1) (write 1 only or read) 0: in packet is not ready 1: in packet is ready in0csr2 send_stall bit (bit 2) (write 1 only or read) 0: no action 1: stall endpoint 0 by the cpu in0csr3 data_end bit (bit 3) (write 1 only or read) 0: no action 1: last packet of data transferred from/to the fifo in0csr4 force_stall flag (bit 4) (write 0 only or read) 0: no action 1: stall endpoint 0 by the usb fcu in0csr5 setup_end flag (bit 5) (read only - write 0) 0: no action 1: control transfer ended before the speci?c length of data is transferred during the data phase in0csr6 serviced_out_pkt_rdy bit (bit 6) (write only - read 0) 0: no change 1: clear the out_pkt_rdy bit (in0csr0) in0csr7 serviced_setup_end bit (bit 7) (write only - read 0) 0: no change 1: clear the stup_end bit (in0csr5) msb 7 lsb 0 in0csr7 in0csr6 in0csr5 in0csr4 in0csr3 in0csr1 in0csr0 access: r/w reset: 00 16 in0csr2 address: 0059 16
5-18 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-42. endpoints 1, 2, 3, 4 in csr figure 5-43. endpoint 0 out csr figure 5-44. endpoint 1, 2, 3, 4 out csr inxcsr0 in_pkt_rdy bit (bit 0) (write 1 only or read) 0: in packet is not ready 1: in packet is ready inxcsr1 under_run flag (bit 1) (write 0 only or read) 0: no fifo underrun 1: fifo underrun has occurred inxcsr2 send_stall bit (bit 2) 0: no action 1: stall in endpoint x by the cpu inxcsr3 iso bit (bit 3) 0: select non-isochronous transfer 1: select isochronous transfer inxcsr4 intpt bit (bit 4) 0: select non-rate feedback interrupt transfer 1: select rate feedback interrupt transfer inxcsr5 tx_not_ept flag (bit 5) (read only - write 0) 0: transmit fifo is empty 1: transmit fifo is not empty inxcsr6 flush bit (bit 6) (write only - read 0) 0: no action 1: flush the fifo inxcsr7 auto_set bit (bit 7) 0: auto_set disabled 1: auto_set enabled msb 7 lsb 0 inxcsr7 inxcsr6 inxcsr5 inxcsr4 inxcsr3 inxcsr1 inxcsr0 access: r/w reset: 00 16 inxcsr2 address: 0059 16 bits 7:0 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved reserved reserved access: r reset: 00 16 address: 005a 16 reserved outxcsr0 out_pkt_rdy flag (bit 0) (write 0 only or read) 0: out packet is not ready 1: out packet is ready outxcsr1 over_run flag (bit 1) (write 0 only or read) 0: no fifo overrun 1: fifo overrun occurred outxcsr2 send_stall bit (bit 2) 0: no action 1: stall out endpoint x by the cpu outxcsr3 iso bit (bit 3) 0: select non-isochronous transfer 1: select isochronous transfer outxcsr4 force_stall flag (bit 4) (write 0 only or read) 0: no action 1: stall endpoint x by the usb fcu outxcsr5 data_err flag (bit 5) (write 0 only or read) 0: no error 1: crc or bit stuf?ng error received in an iso packet outxcsr6 flush bit (bit 6) (write only - read 0) 0: no action 1: flush the fifo outxcsr7 auto_clr bit (bit 7) 0: auto_clr disabled 1: auto_clr enabled msb 7 lsb 0 outxcsr7 outxcsr6 outxcsr5 outxcsr4 outxcsr3 outxcsr1 outxcsr0 access: r/w reset: 00 16 outxcsr2 address: 005a 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-19 figure 5-45. endpoint x in maxp figure 5-46. endpoint x out maxp figure 5-47. endpoint 0, 1, 2, 3, 4 out write count register low figure 5-48. endpoint 0, 1, 2, 3, 4 out write count register high figure 5-49. endpoint 0 fifo register figure 5-50. endpoint 1 fifo register figure 5-51. endpoint 2 fifo register imaxp7:0 maximum packet size (maxp) of endpoint x in packet. maxp = n for endpoints 0, 2, 3, 4 maxp = n * 8 for endpoint 1 n is the value written to this register. for endpoints that support a smaller fifo size, unused bits are not implemented (always write 0 to those bits) msb 7 lsb 0 imaxp7 imaxp6 imaxp5 imaxp4 imaxp3 imaxp1 imaxp0 access: r/w imaxp2 address: 005b 16 omaxp7:0 maximum packet size (maxp) of endpoint x out packet. maxp = n for endpoints 2, 3, 4 maxp = n * 8 for endpoint 1 n is the value written to this register. for endpoints that support a smaller fifo size, unused bits are not implemented (always write 0 to those bits) msb 7 lsb 0 omaxp7 omaxp6 omaxp5 omaxp4 omaxp3 omaxp1 omaxp0 access: r/w omaxp2 address: 005c 16 w_cnt7:0 byte count. this register contains the lower 8 bits of the byte count register msb 7 lsb 0 w_cnt7 w_cnt6 w_cnt5 w_cnt4 w_cnt3 w_cnt1 w_cnt0 access: r reset: 00 16 w_cnt2 address: 005d 16 w_cnt9:8 byte count. this register contains the upper 2 bits of the byte count register bits 7:2 reserved (read 0) msb 7 lsb 0 reserved reserved reserved reserved reserved w_cnt9 w_cnt8 access: r reset: 00 16 address: 005e 16 reserved data_7:0 endpoint 0 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0060 16 data_7:0 endpoint 1 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0061 16 data_7:0 endpoint 2 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0062 16
5-20 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers figure 5-52. endpoint 3 fifo register figure 5-53. endpoint 4 fifo register figure 5-54. frequency synthesizer control register figure 5-55. frequency synthesizer multiply control register fsm1 data_7:0 endpoint 3 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0063 16 data_7:0 endpoint 4 in/out fifo register msb 7 lsb 0 data_7 data_6 data_5 data_4 data_3 data_1 data_0 access: r/w reset: n/a data_2 address: 0064 16 fse frequency synthesizer enable bit (bit 0) 0: disabled 1: enabled vco1,0 vco gain control (bits 2,1) bit 2 bit 1 0 0: lowest gain (recommended) 0 1: low gain 1 0: high gain 1 1: highest gain fin frequency synthesizer input selector bit (bit 3) 0: x in 1: xc in bit 4 reserved (read/write 0) chg1,0 lpf current control (bits 6,5) bit 6 bit 5 0 0: disabled 0 1: low current 1 0: intermediate current (recommended) 1 1: high current ls frequency synthesizer lock status bit (bit 7) (read only; write 0) 0: unlocked 1: locked msb 7 lsb 0 chg0 fin vco0 fse address: 006c 16 access: r/w reset: 60 16 vco1 ls chg1 reserved f vco /2( n +1) = f pin f pin fsm1 f vco dec(n) hex(n) 320 khz 74 4a 48.00 mhz 2 mhz 11 0b 48.00 mhz 4 mhz 5 05 48.00 mhz 6 mhz 3 03 48.00 mhz 12 mhz 1 01 48.00 mhz 24 mhz 0 00 48.00 mhz msb 7 lsb 0 bit 6 bit 1 bit 0 bit 2 bit 5 bit 4 bit 3 bit 7 address: 006d 16 access: r/w reset: ff 16
7600 series mitsubishi microcomputer m37640e8-xxxf preliminary specification 6/2/98 5-21 figure 5-56. frequency synthesizer multiply control register fsm2 figure 5-57. frequency synthesizer divide register f in /2( n +1) = f pin f pin fsm2 f in dec(n) hex(n) 24 mhz 255 ff 24.00 mhz 1 mhz 11 0c 24.00 mhz 2 mhz 5 05 24.00 mhz 3 mhz 3 03 24.00 mhz 6 mhz 1 01 24.00 mhz 12 mhz 0 00 24.00 mhz msb 7 lsb 0 bit 6 bit 1 bit 0 bit 2 bit 5 bit 4 bit 3 bit 7 access: r/w address: 006e 16 reset: ff 16 f vco /2(m+1) = f syn f vco fsd f syn dec(m) hex(m) 48.00 mhz 00 00 24.00 mhz 48.00 mhz 127 7f 187.50 khz msb 7 lsb 0 bit 6 bit 1 bit 0 address: 006f 16 access: r/w reset: ff 16 bit 2 bit 5 bit 4 bit 3 bit 7
5-22 6/2/98 7600 series m37640e8-xxxf preliminary specification mitsubishi microcomputers

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